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target/arm: Clear high SVE elements in handle_vec_simd_wshli

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AdvSIMD instructions are supposed to zero bits beyond 128.
Affects SSHLL, USHLL, SSHLL2, USHLL2.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240717060903.205098-15-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson 2024-08-13 11:42:49 +01:00 committed by Peter Maydell
parent 20516e8d0e
commit 8e0c9a9efa
1 changed files with 1 additions and 0 deletions
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target/arm/tcg/translate-a64.c
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@ -10756,6 +10756,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
write_vec_element(s, tcg_rd, rd, i, size + 1); write_vec_element(s, tcg_rd, rd, i, size + 1);
} }
clear_vec_high(s, true, rd);
} }
/* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */