target/mips: Fix gdbstub to read/write 64 bit FP registers
Fix gdbstub to read/write 64 bit FP registers Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
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@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
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return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
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default:
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default:
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if (env->CP0_Status & (1 << CP0St_FR)) {
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if (env->CP0_Status & (1 << CP0St_FR)) {
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return gdb_get_regl(mem_buf,
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return gdb_get_reg64(mem_buf,
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env->active_fpu.fpr[n - 38].d);
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env->active_fpu.fpr[n - 38].d);
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} else {
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} else {
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return gdb_get_regl(mem_buf,
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return gdb_get_regl(mem_buf,
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@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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break;
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break;
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default:
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default:
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if (env->CP0_Status & (1 << CP0St_FR)) {
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if (env->CP0_Status & (1 << CP0St_FR)) {
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uint64_t tmp = ldq_p(mem_buf);
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env->active_fpu.fpr[n - 38].d = tmp;
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env->active_fpu.fpr[n - 38].d = tmp;
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} else {
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} else {
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env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
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env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
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