target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2021,6 +2021,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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valid_mask |= SCR_API | SCR_APK;
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valid_mask |= SCR_API | SCR_APK;
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}
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}
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if (cpu_isar_feature(aa64_mte, cpu)) {
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valid_mask |= SCR_ATA;
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}
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} else {
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} else {
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valid_mask &= ~(SCR_RW | SCR_ST);
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valid_mask &= ~(SCR_RW | SCR_ST);
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}
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}
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@ -5248,17 +5251,22 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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valid_mask |= HCR_API | HCR_APK;
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valid_mask |= HCR_API | HCR_APK;
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}
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}
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if (cpu_isar_feature(aa64_mte, cpu)) {
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valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
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}
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}
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}
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/* Clear RES0 bits. */
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/* Clear RES0 bits. */
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value &= valid_mask;
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value &= valid_mask;
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/* These bits change the MMU setup:
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/*
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* These bits change the MMU setup:
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* HCR_VM enables stage 2 translation
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* HCR_VM enables stage 2 translation
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* HCR_PTW forbids certain page-table setups
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* HCR_PTW forbids certain page-table setups
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* HCR_DC Disables stage1 and enables stage2 translation
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* HCR_DC disables stage1 and enables stage2 translation
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* HCR_DCT enables tagging on (disabled) stage1 translation
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*/
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*/
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if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
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if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) {
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tlb_flush(CPU(cpu));
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tlb_flush(CPU(cpu));
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}
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}
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env->cp15.hcr_el2 = value;
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env->cp15.hcr_el2 = value;
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