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target/arm: Convert MLA, MLS to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-28 13:30:40 -07:00 committed by Peter Maydell
parent b73c7b1740
commit 8db93dcd3d
2 changed files with 31 additions and 54 deletions
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8
target/arm/tcg/a64.decode
View File

@ -928,6 +928,8 @@ SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e
UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e
MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e
PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b
MLA_v 0.00 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e
MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e
### Advanced SIMD scalar x indexed element ### Advanced SIMD scalar x indexed element
@ -972,3 +974,9 @@ FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h
MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h
MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s
MLA_vi 0.10 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h
MLA_vi 0.10 1111 10 . ..... 0000 . 0 ..... ..... @qrrx_s
MLS_vi 0.10 1111 01 .. .... 0100 . 0 ..... ..... @qrrx_h
MLS_vi 0.10 1111 10 . ..... 0100 . 0 ..... ..... @qrrx_s

77
target/arm/tcg/translate-a64.c
View File

@ -5470,6 +5470,8 @@ TRANS(SABD_v, do_gvec_fn3_no64, a, gen_gvec_sabd)
TRANS(UABD_v, do_gvec_fn3_no64, a, gen_gvec_uabd) TRANS(UABD_v, do_gvec_fn3_no64, a, gen_gvec_uabd)
TRANS(MUL_v, do_gvec_fn3_no64, a, tcg_gen_gvec_mul) TRANS(MUL_v, do_gvec_fn3_no64, a, tcg_gen_gvec_mul)
TRANS(PMUL_v, do_gvec_op3_ool, a, 0, gen_helper_gvec_pmul_b) TRANS(PMUL_v, do_gvec_op3_ool, a, 0, gen_helper_gvec_pmul_b)
TRANS(MLA_v, do_gvec_fn3_no64, a, gen_gvec_mla)
TRANS(MLS_v, do_gvec_fn3_no64, a, gen_gvec_mls)
static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond) static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond)
{ {
@ -5712,6 +5714,24 @@ static gen_helper_gvec_3 * const f_vector_idx_mul[2] = {
}; };
TRANS(MUL_vi, do_int3_vector_idx, a, f_vector_idx_mul) TRANS(MUL_vi, do_int3_vector_idx, a, f_vector_idx_mul)
static bool do_mla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool sub)
{
static gen_helper_gvec_4 * const fns[2][2] = {
{ gen_helper_gvec_mla_idx_h, gen_helper_gvec_mls_idx_h },
{ gen_helper_gvec_mla_idx_s, gen_helper_gvec_mls_idx_s },
};
assert(a->esz == MO_16 || a->esz == MO_32);
if (fp_access_check(s)) {
gen_gvec_op4_ool(s, a->q, a->rd, a->rn, a->rm, a->rd,
a->idx, fns[a->esz - 1][sub]);
}
return true;
}
TRANS(MLA_vi, do_mla_vector_idx, a, false)
TRANS(MLS_vi, do_mla_vector_idx, a, true)
/* /*
* Advanced SIMD scalar pairwise * Advanced SIMD scalar pairwise
*/ */
@ -10945,12 +10965,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rd = extract32(insn, 0, 5); int rd = extract32(insn, 0, 5);
switch (opcode) { switch (opcode) {
case 0x12: /* MLA, MLS */
if (size == 3) {
unallocated_encoding(s);
return;
}
break;
case 0x16: /* SQDMULH, SQRDMULH */ case 0x16: /* SQDMULH, SQRDMULH */
if (size == 0 || size == 3) { if (size == 0 || size == 3) {
unallocated_encoding(s); unallocated_encoding(s);
@ -10981,6 +10995,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
case 0x0f: /* SABA, UABA */ case 0x0f: /* SABA, UABA */
case 0x10: /* ADD, SUB */ case 0x10: /* ADD, SUB */
case 0x11: /* CMTST, CMEQ */ case 0x11: /* CMTST, CMEQ */
case 0x12: /* MLA, MLS */
case 0x13: /* MUL, PMUL */ case 0x13: /* MUL, PMUL */
unallocated_encoding(s); unallocated_encoding(s);
return; return;
@ -10991,13 +11006,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
} }
switch (opcode) { switch (opcode) {
case 0x12: /* MLA, MLS */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
}
return;
case 0x16: /* SQDMULH, SQRDMULH */ case 0x16: /* SQDMULH, SQRDMULH */
{ {
static gen_helper_gvec_3_ptr * const fns[2][2] = { static gen_helper_gvec_3_ptr * const fns[2][2] = {
@ -12204,13 +12212,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
TCGv_ptr fpst; TCGv_ptr fpst;
switch (16 * u + opcode) { switch (16 * u + opcode) {
case 0x10: /* MLA */
case 0x14: /* MLS */
if (is_scalar) {
unallocated_encoding(s);
return;
}
break;
case 0x02: /* SMLAL, SMLAL2 */ case 0x02: /* SMLAL, SMLAL2 */
case 0x12: /* UMLAL, UMLAL2 */ case 0x12: /* UMLAL, UMLAL2 */
case 0x06: /* SMLSL, SMLSL2 */ case 0x06: /* SMLSL, SMLSL2 */
@ -12292,6 +12293,8 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
case 0x05: /* FMLS */ case 0x05: /* FMLS */
case 0x08: /* MUL */ case 0x08: /* MUL */
case 0x09: /* FMUL */ case 0x09: /* FMUL */
case 0x10: /* MLA */
case 0x14: /* MLS */
case 0x18: /* FMLAL2 */ case 0x18: /* FMLAL2 */
case 0x19: /* FMULX */ case 0x19: /* FMULX */
case 0x1c: /* FMLSL2 */ case 0x1c: /* FMLSL2 */
@ -12412,40 +12415,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
: gen_helper_gvec_fcmlah_idx); : gen_helper_gvec_fcmlah_idx);
} }
return; return;
case 0x10: /* MLA */
if (!is_long && !is_scalar) {
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_gvec_mla_idx_h,
gen_helper_gvec_mla_idx_s,
gen_helper_gvec_mla_idx_d,
};
tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
case 0x14: /* MLS */
if (!is_long && !is_scalar) {
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_gvec_mls_idx_h,
gen_helper_gvec_mls_idx_s,
gen_helper_gvec_mls_idx_d,
};
tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
} }
if (size == 3) { if (size == 3) {