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target-ppc: better support of e300 CPU core

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Declare HID2 register.

Use high BATs for e300 (8 instead of 4).

Fix index of high BATs registers.
Before the fix, IBAT4-7 were overwriting IBAT0-3.

Signed-off-by: François Armand <francois.armand@os4i.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Thomas Monjalon 2009-10-15 19:01:19 +02:00 committed by Aurelien Jarno
parent dcc65026c4
commit 8daf178168
1 changed files with 8 additions and 2 deletions
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10
target-ppc/translate_init.c
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@ -233,7 +233,7 @@ static void spr_write_ibatu (void *opaque, int sprn, int gprn)
static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
{ {
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2); TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
gen_helper_store_ibatu(t0, cpu_gpr[gprn]); gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
} }
@ -247,7 +247,7 @@ static void spr_write_ibatl (void *opaque, int sprn, int gprn)
static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
{ {
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2); TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
gen_helper_store_ibatl(t0, cpu_gpr[gprn]); gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
} }
@ -4166,8 +4166,14 @@ static void init_proc_e300 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic, &spr_read_generic, &spr_write_generic,
0x00000000); 0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */ /* Memory management */
gen_low_BATs(env); gen_low_BATs(env);
gen_high_BATs(env);
gen_6xx_7xx_soft_tlb(env, 64, 2); gen_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env); init_excp_603(env);
env->dcache_line_size = 32; env->dcache_line_size = 32;