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hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers

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The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.

Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-3-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-03-04 19:25:11 +01:00
parent 260290677e
commit 8d492c5f06
1 changed files with 6 additions and 4 deletions
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10
hw/mips/gt64xxx_pci.c
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@ -385,13 +385,12 @@ static void gt64120_writel(void *opaque, hwaddr addr,
{ {
GT64120State *s = opaque; GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s); PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t saddr; uint32_t saddr = addr >> 2;
if (!(s->regs[GT_CPU] & 0x00001000)) { if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val); val = bswap32(val);
} }
saddr = (addr & 0xfff) >> 2;
switch (saddr) { switch (saddr) {
/* CPU Configuration */ /* CPU Configuration */
@ -695,9 +694,8 @@ static uint64_t gt64120_readl(void *opaque,
GT64120State *s = opaque; GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s); PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val; uint32_t val;
uint32_t saddr; uint32_t saddr = addr >> 2;
saddr = (addr & 0xfff) >> 2;
switch (saddr) { switch (saddr) {
/* CPU Configuration */ /* CPU Configuration */
@ -976,6 +974,10 @@ static const MemoryRegionOps isd_mem_ops = {
.read = gt64120_readl, .read = gt64120_readl,
.write = gt64120_writel, .write = gt64120_writel,
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
}; };
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)