target/sh4: Fix code style for checkpatch.pl
We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210127232151.3523581-2-f4bug@amsat.org>
This commit is contained in:
parent
91e92cad67
commit
8d2b06fbc2
@ -330,8 +330,8 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid
|
||||
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
|
||||
*/
|
||||
static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
|
||||
int *prot, target_ulong address,
|
||||
int rw, int access_type)
|
||||
int *prot, target_ulong address,
|
||||
int rw, int access_type)
|
||||
{
|
||||
int use_asid, n;
|
||||
tlb_t *matching = NULL;
|
||||
@ -340,12 +340,12 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
|
||||
|
||||
if (rw == 2) {
|
||||
n = find_itlb_entry(env, address, use_asid);
|
||||
if (n >= 0) {
|
||||
matching = &env->itlb[n];
|
||||
if (n >= 0) {
|
||||
matching = &env->itlb[n];
|
||||
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
||||
n = MMU_ITLB_VIOLATION;
|
||||
n = MMU_ITLB_VIOLATION;
|
||||
} else {
|
||||
*prot = PAGE_EXEC;
|
||||
*prot = PAGE_EXEC;
|
||||
}
|
||||
} else {
|
||||
n = find_utlb_entry(env, address, use_asid);
|
||||
@ -365,14 +365,14 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
|
||||
} else if (n == MMU_DTLB_MISS) {
|
||||
n = MMU_ITLB_MISS;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
n = find_utlb_entry(env, address, use_asid);
|
||||
if (n >= 0) {
|
||||
matching = &env->utlb[n];
|
||||
n = find_utlb_entry(env, address, use_asid);
|
||||
if (n >= 0) {
|
||||
matching = &env->utlb[n];
|
||||
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
||||
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
||||
MMU_DTLB_VIOLATION_READ;
|
||||
n = (rw == 1)
|
||||
? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ;
|
||||
} else if ((rw == 1) && !(matching->pr & 1)) {
|
||||
n = MMU_DTLB_VIOLATION_WRITE;
|
||||
} else if ((rw == 1) && !matching->d) {
|
||||
@ -383,15 +383,15 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
|
||||
*prot |= PAGE_WRITE;
|
||||
}
|
||||
}
|
||||
} else if (n == MMU_DTLB_MISS) {
|
||||
n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
|
||||
MMU_DTLB_MISS_READ;
|
||||
}
|
||||
} else if (n == MMU_DTLB_MISS) {
|
||||
n = (rw == 1)
|
||||
? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ;
|
||||
}
|
||||
}
|
||||
if (n >= 0) {
|
||||
n = MMU_OK;
|
||||
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
|
||||
(address & (matching->size - 1));
|
||||
n = MMU_OK;
|
||||
*physical = ((matching->ppn << 10) & ~(matching->size - 1))
|
||||
| (address & (matching->size - 1));
|
||||
}
|
||||
return n;
|
||||
}
|
||||
@ -401,34 +401,34 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
|
||||
int rw, int access_type)
|
||||
{
|
||||
/* P1, P2 and P4 areas do not use translation */
|
||||
if ((address >= 0x80000000 && address < 0xc0000000) ||
|
||||
address >= 0xe0000000) {
|
||||
if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) {
|
||||
if (!(env->sr & (1u << SR_MD))
|
||||
&& (address < 0xe0000000 || address >= 0xe4000000)) {
|
||||
/* Unauthorized access in user mode (only store queues are available) */
|
||||
&& (address < 0xe0000000 || address >= 0xe4000000)) {
|
||||
/* Unauthorized access in user mode (only store queues are available) */
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
|
||||
if (rw == 0)
|
||||
return MMU_DADDR_ERROR_READ;
|
||||
else if (rw == 1)
|
||||
return MMU_DADDR_ERROR_WRITE;
|
||||
else
|
||||
return MMU_IADDR_ERROR;
|
||||
}
|
||||
if (address >= 0x80000000 && address < 0xc0000000) {
|
||||
/* Mask upper 3 bits for P1 and P2 areas */
|
||||
*physical = address & 0x1fffffff;
|
||||
} else {
|
||||
*physical = address;
|
||||
}
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return MMU_OK;
|
||||
if (rw == 0) {
|
||||
return MMU_DADDR_ERROR_READ;
|
||||
} else if (rw == 1) {
|
||||
return MMU_DADDR_ERROR_WRITE;
|
||||
} else {
|
||||
return MMU_IADDR_ERROR;
|
||||
}
|
||||
}
|
||||
if (address >= 0x80000000 && address < 0xc0000000) {
|
||||
/* Mask upper 3 bits for P1 and P2 areas */
|
||||
*physical = address & 0x1fffffff;
|
||||
} else {
|
||||
*physical = address;
|
||||
}
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return MMU_OK;
|
||||
}
|
||||
|
||||
/* If MMU is disabled, return the corresponding physical page */
|
||||
if (!(env->mmucr & MMUCR_AT)) {
|
||||
*physical = address & 0x1FFFFFFF;
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return MMU_OK;
|
||||
*physical = address & 0x1FFFFFFF;
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return MMU_OK;
|
||||
}
|
||||
|
||||
/* We need to resort to the MMU */
|
||||
|
Loading…
Reference in New Issue
Block a user