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i.MX: Standardize i.MX serial debug.

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The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 47b8759b251d356c633faf7ea34f897f340aea4e.1445781957.git.jcd@tribudubois.net
[PMM: Drop attempt to print the ram_addr of a memory region in
 one DPRINTF, which (a) was using the wrong format string so
 didn't build on 32-bit and (b) was incorrectly looking at a
 private field of a MemoryRegion struct]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe Dubois 2015-10-25 15:16:06 +01:00 committed by Peter Maydell
parent 4b280b726a
commit 8ccce77c04
1 changed files with 24 additions and 26 deletions
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50
hw/char/imx_serial.c
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@ -22,25 +22,17 @@
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "sysemu/char.h" #include "sysemu/char.h"
//#define DEBUG_SERIAL 1 #ifndef DEBUG_IMX_UART
#ifdef DEBUG_SERIAL #define DEBUG_IMX_UART 0
#define DPRINTF(fmt, args...) \
do { printf("%s: " fmt , TYPE_IMX_SERIAL, ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif #endif
/* #define DPRINTF(fmt, args...) \
* Define to 1 for messages about attempts to do { \
* access unimplemented registers or similar. if (DEBUG_IMX_UART) { \
*/ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
//#define DEBUG_IMPLEMENTATION 1 __func__, ##args); \
#ifdef DEBUG_IMPLEMENTATION } \
# define IPRINTF(fmt, args...) \ } while (0)
do { fprintf(stderr, "%s: " fmt, TYPE_IMX_SERIAL, ##args); } while (0)
#else
# define IPRINTF(fmt, args...) do {} while (0)
#endif
static const VMStateDescription vmstate_imx_serial = { static const VMStateDescription vmstate_imx_serial = {
.name = TYPE_IMX_SERIAL, .name = TYPE_IMX_SERIAL,
@ -115,7 +107,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
IMXSerialState *s = (IMXSerialState *)opaque; IMXSerialState *s = (IMXSerialState *)opaque;
uint32_t c; uint32_t c;
DPRINTF("read(offset=%x)\n", offset >> 2); DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
switch (offset >> 2) { switch (offset >> 2) {
case 0x0: /* URXD */ case 0x0: /* URXD */
c = s->readbuff; c = s->readbuff;
@ -167,7 +160,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
return 0x0; /* TODO */ return 0x0; /* TODO */
default: default:
IPRINTF("%s: bad offset: 0x%x\n", __func__, (int)offset); qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
return 0; return 0;
} }
} }
@ -178,9 +172,8 @@ static void imx_serial_write(void *opaque, hwaddr offset,
IMXSerialState *s = (IMXSerialState *)opaque; IMXSerialState *s = (IMXSerialState *)opaque;
unsigned char ch; unsigned char ch;
DPRINTF("write(offset=%x, value = %x) to %s\n", DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
offset >> 2, offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV");
(unsigned int)value, s->chr ? s->chr->label : "NODEV");
switch (offset >> 2) { switch (offset >> 2) {
case 0x10: /* UTXD */ case 0x10: /* UTXD */
@ -198,7 +191,9 @@ static void imx_serial_write(void *opaque, hwaddr offset,
case 0x20: /* UCR1 */ case 0x20: /* UCR1 */
s->ucr1 = value & 0xffff; s->ucr1 = value & 0xffff;
DPRINTF("write(ucr1=%x)\n", (unsigned int)value); DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
imx_update(s); imx_update(s);
break; break;
@ -266,12 +261,14 @@ static void imx_serial_write(void *opaque, hwaddr offset,
case 0x2d: /* UTS1 */ case 0x2d: /* UTS1 */
case 0x23: /* UCR4 */ case 0x23: /* UCR4 */
IPRINTF("Unimplemented Register %x written to\n", offset >> 2); qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
/* TODO */ /* TODO */
break; break;
default: default:
IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset); qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
} }
} }
@ -284,7 +281,9 @@ static int imx_can_receive(void *opaque)
static void imx_put_data(void *opaque, uint32_t value) static void imx_put_data(void *opaque, uint32_t value)
{ {
IMXSerialState *s = (IMXSerialState *)opaque; IMXSerialState *s = (IMXSerialState *)opaque;
DPRINTF("received char\n"); DPRINTF("received char\n");
s->usr1 |= USR1_RRDY; s->usr1 |= USR1_RRDY;
s->usr2 |= USR2_RDR; s->usr2 |= USR2_RDR;
s->uts1 &= ~UTS1_RXEMPTY; s->uts1 &= ~UTS1_RXEMPTY;
@ -319,8 +318,7 @@ static void imx_serial_realize(DeviceState *dev, Error **errp)
qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
imx_event, s); imx_event, s);
} else { } else {
DPRINTF("No char dev for uart at 0x%lx\n", DPRINTF("No char dev for uart\n");
(unsigned long)s->iomem.ram_addr);
} }
} }