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Various improvements to the qtest checks:

Browse Source 
- Clean-ups by Eric Blake with regards to the global_qtest variable
 - Some more test cases for the boot-serial tester
 - Re-activation of the m48t59-test
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Merge remote-tracking branch 'remotes/huth/tags/pull-request-2018-02-14' into staging

Various improvements to the qtest checks:
- Clean-ups by Eric Blake with regards to the global_qtest variable
- Some more test cases for the boot-serial tester
- Re-activation of the m48t59-test

# gpg: Signature made Wed 14 Feb 2018 11:07:44 GMT
# gpg:                using RSA key 2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>"
# gpg:                 aka "Thomas Huth <thuth@redhat.com>"
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>"
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>"
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* remotes/huth/tags/pull-request-2018-02-14:
  tests/m48t59: Use the m48t59 test on ppc, too
  tests/Makefile: Derive check-qtest-ppc64-y from check-qtest-ppc-y
  tests/m48t59: Make the test independent of global_qtest
  tests/m48t59: Fix and re-enable the test for sparc
  tests/boot-serial-test: Add support for the aarch64 virt machine
  tests/boot-serial: Add tests for PowerPC Mac machines
  tests/boot-serial: Enable the boot-serial test on SPARC machines, too
  wdt_ib700-test: Drop dependence on global_qtest
  tests/boot-sector: Drop dependence on global_qtest
  qmp-test: Drop dependence on global_qtest
  libqos: Use explicit QTestState for remaining libqos operations
  libqos: Use explicit QTestState for ahci operations
  libqos: Use explicit QTestState for i2c operations
  libqos: Use explicit QTestState for rtas operations
  libqos: Use explicit QTestState for fw_cfg operations
  libqos: Track QTestState with QPCIBus
  libqtest: Use qemu_strtoul()
  tests: Clean up wait for event

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-02-15 13:00:44 +00:00
commit 8c5e7bddc2
55 changed files with 416 additions and 374 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
tests/Makefile.include
View File

@ -319,16 +319,15 @@ check-qtest-ppc-y += tests/boot-order-test$(EXESUF)
check-qtest-ppc-y += tests/prom-env-test$(EXESUF)
check-qtest-ppc-y += tests/drive_del-test$(EXESUF)
check-qtest-ppc-y += tests/boot-serial-test$(EXESUF)
check-qtest-ppc-y += tests/m48t59-test$(EXESUF)
gcov-files-ppc-y += hw/timer/m48t59.c
check-qtest-ppc64-y = tests/spapr-phb-test$(EXESUF)
gcov-files-ppc64-y = ppc64-softmmu/hw/ppc/spapr_pci.c
check-qtest-ppc64-y += tests/endianness-test$(EXESUF)
check-qtest-ppc64-y += tests/boot-order-test$(EXESUF)
check-qtest-ppc64-y += tests/prom-env-test$(EXESUF)
check-qtest-ppc64-y = $(check-qtest-ppc-y)
gcov-files-ppc64-y = $(subst ppc-softmmu/,ppc64-softmmu/,$(gcov-files-ppc-y))
check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF)
gcov-files-ppc64-y += ppc64-softmmu/hw/ppc/spapr_pci.c
check-qtest-ppc64-y += tests/pnv-xscom-test$(EXESUF)
check-qtest-ppc64-y += tests/drive_del-test$(EXESUF)
check-qtest-ppc64-y += tests/migration-test$(EXESUF)
check-qtest-ppc64-y += tests/boot-serial-test$(EXESUF)
check-qtest-ppc64-y += tests/rtas-test$(EXESUF)
check-qtest-ppc64-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF)
check-qtest-ppc64-y += tests/usb-hcd-ohci-test$(EXESUF)
@ -351,13 +350,13 @@ check-qtest-sh4-y = tests/endianness-test$(EXESUF)
check-qtest-sh4eb-y = tests/endianness-test$(EXESUF)
check-qtest-sparc-y = tests/prom-env-test$(EXESUF)
#check-qtest-sparc-y += tests/m48t59-test$(EXESUF)
#gcov-files-sparc-y = hw/timer/m48t59.c
check-qtest-sparc-y += tests/m48t59-test$(EXESUF)
gcov-files-sparc-y = hw/timer/m48t59.c
check-qtest-sparc-y += tests/boot-serial-test$(EXESUF)
check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
#check-qtest-sparc64-y += tests/m48t59-test$(EXESUF)
#gcov-files-sparc64-y += hw/timer/m48t59.c
check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
@ -372,6 +371,7 @@ check-qtest-arm-y += tests/sdhci-test$(EXESUF)
check-qtest-aarch64-y = tests/numa-test$(EXESUF)
check-qtest-aarch64-y += tests/sdhci-test$(EXESUF)
check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
check-qtest-microblazeel-y = $(check-qtest-microblaze-y)

3
tests/ahci-test.c
View File

@ -158,10 +158,11 @@ static AHCIQState *ahci_vboot(const char *cli, va_list ap)
s = g_new0(AHCIQState, 1);
s->parent = qtest_pc_vboot(cli, ap);
global_qtest = s->parent->qts;
alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
/* Verify that we have an AHCI device present. */
s->dev = get_ahci_device(&s->fingerprint);
s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
return s;
}

2
tests/bios-tables-test.c
View File

@ -668,7 +668,7 @@ static void test_acpi_one(const char *params, test_data *data)
qtest_start(args);
boot_sector_test();
boot_sector_test(global_qtest);
data->tables = g_array_new(false, true, sizeof(AcpiSdtTable));
test_acpi_rsdp_address(data);

8
tests/boot-order-test.c
View File

@ -41,7 +41,7 @@ static void test_a_boot_order(const char *machine,
* system_reset only requests reset. We get a RESET event after
* the actual reset completes. Need to wait for that.
*/
qmp_discard_response(""); /* HACK: wait for event */
qmp_eventwait("RESET");
actual = read_boot_order();
g_assert_cmphex(actual, ==, expected_reboot);
qtest_quit(global_qtest);
@ -132,7 +132,7 @@ static void test_prep_boot_order(void)
static uint64_t read_boot_order_pmac(void)
{
QFWCFG *fw_cfg = mm_fw_cfg_init(0xf0000510);
QFWCFG *fw_cfg = mm_fw_cfg_init(global_qtest, 0xf0000510);
return qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_DEVICE);
}
@ -157,7 +157,7 @@ static void test_pmac_newworld_boot_order(void)
static uint64_t read_boot_order_sun4m(void)
{
QFWCFG *fw_cfg = mm_fw_cfg_init(0xd00000510ULL);
QFWCFG *fw_cfg = mm_fw_cfg_init(global_qtest, 0xd00000510ULL);
return qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_DEVICE);
}
@ -169,7 +169,7 @@ static void test_sun4m_boot_order(void)
static uint64_t read_boot_order_sun4u(void)
{
QFWCFG *fw_cfg = io_fw_cfg_init(0x510);
QFWCFG *fw_cfg = io_fw_cfg_init(global_qtest, 0x510);
return qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_DEVICE);
}

8
tests/boot-sector.c
View File

@ -5,7 +5,7 @@
*
* Authors:
* Michael S. Tsirkin <mst@redhat.com>
* Victor Kaplansky <victork@redhat.com>
* Victor Kaplansky <victork@redhat.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@ -130,7 +130,7 @@ int boot_sector_init(char *fname)
}
/* Loop until signature in memory is OK. */
void boot_sector_test(void)
void boot_sector_test(QTestState *qts)
{
uint8_t signature_low;
uint8_t signature_high;
@ -146,8 +146,8 @@ void boot_sector_test(void)
* instruction.
*/
for (i = 0; i < TEST_CYCLES; ++i) {
signature_low = readb(SIGNATURE_ADDR);
signature_high = readb(SIGNATURE_ADDR + 1);
signature_low = qtest_readb(qts, SIGNATURE_ADDR);
signature_high = qtest_readb(qts, SIGNATURE_ADDR + 1);
signature = (signature_high << 8) | signature_low;
if (signature == SIGNATURE) {
break;

6
tests/boot-sector.h
View File

@ -5,7 +5,7 @@
*
* Authors:
* Michael S. Tsirkin <mst@redhat.com>
* Victor Kaplansky <victork@redhat.com>
* Victor Kaplansky <victork@redhat.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@ -14,11 +14,13 @@
#ifndef TEST_BOOT_SECTOR_H
#define TEST_BOOT_SECTOR_H
#include "libqtest.h"
/* Create boot disk file. fname must be a suitable string for mkstemp() */
int boot_sector_init(char *fname);
/* Loop until signature in memory is OK. */
void boot_sector_test(void);
void boot_sector_test(QTestState *qts);
/* unlink boot disk file. */
void boot_sector_cleanup(const char *fname);

16
tests/boot-serial-test.c
View File

@ -55,6 +55,13 @@ static const uint8_t bios_raspi2[] = {
0x00, 0x10, 0x20, 0x3f, /* 0x3f201000 = UART0 base addr */
};
static const uint8_t kernel_aarch64[] = {
0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */
0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 */
0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] */
0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
};
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
@ -69,8 +76,11 @@ static testdef_t tests[] = {
{ "alpha", "clipper", "", "PCI:" },
{ "ppc", "ppce500", "", "U-Boot" },
{ "ppc", "prep", "", "Open Hack'Ware BIOS" },
{ "ppc", "g3beige", "", "PowerPC,750" },
{ "ppc", "mac99", "", "PowerPC,G4" },
{ "ppc64", "ppce500", "", "U-Boot" },
{ "ppc64", "prep", "", "Open Hack'Ware BIOS" },
{ "ppc64", "mac99", "", "PowerPC,970FX" },
{ "ppc64", "pseries", "", "Open Firmware" },
{ "ppc64", "powernv", "-cpu POWER8", "OPAL" },
{ "i386", "isapc", "-cpu qemu32 -device sga", "SGABIOS" },
@ -78,6 +88,10 @@ static testdef_t tests[] = {
{ "i386", "q35", "-device sga", "SGABIOS" },
{ "x86_64", "isapc", "-cpu qemu32 -device sga", "SGABIOS" },
{ "x86_64", "q35", "-device sga", "SGABIOS" },
{ "sparc", "LX", "", "TMS390S10" },
{ "sparc", "SS-4", "", "MB86904" },
{ "sparc", "SS-600MP", "", "TMS390Z55" },
{ "sparc64", "sun4u", "", "UltraSPARC" },
{ "s390x", "s390-ccw-virtio",
"-nodefaults -device sclpconsole,chardev=serial0", "virtio device" },
{ "m68k", "mcf5208evb", "", "TT", sizeof(kernel_mcf5208), kernel_mcf5208 },
@ -88,6 +102,8 @@ static testdef_t tests[] = {
{ "moxie", "moxiesim", "", "TT", sizeof(bios_moxiesim), 0, bios_moxiesim },
{ "arm", "raspi2", "", "TT", sizeof(bios_raspi2), 0, bios_raspi2 },
{ "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
{ "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
{ NULL }
};

6
tests/ds1338-test.c
View File

@ -61,16 +61,14 @@ int main(int argc, char **argv)
g_test_init(&argc, &argv, NULL);
s = qtest_start("-display none -machine imx25-pdk");
i2c = imx_i2c_create(IMX25_I2C_0_BASE);
i2c = imx_i2c_create(s, IMX25_I2C_0_BASE);
addr = DS1338_ADDR;
qtest_add_func("/ds1338/tx-rx", send_and_receive);
ret = g_test_run();
if (s) {
qtest_quit(s);
}
qtest_quit(s);
g_free(i2c);
return ret;

8
tests/e1000e-test.c
View File

@ -392,12 +392,12 @@ static void data_test_init(e1000e_device *d)
qtest_start(cmdline);
g_free(cmdline);
test_bus = qpci_init_pc(NULL);
g_assert_nonnull(test_bus);
test_alloc = pc_alloc_init();
test_alloc = pc_alloc_init(global_qtest);
g_assert_nonnull(test_alloc);
test_bus = qpci_init_pc(global_qtest, test_alloc);
g_assert_nonnull(test_bus);
e1000e_device_init(test_bus, d);
}

13
tests/fw_cfg-test.c
View File

@ -102,12 +102,13 @@ static void test_fw_cfg_boot_menu(void)
int main(int argc, char **argv)
{
QTestState *s;
char *cmdline;
int ret;
g_test_init(&argc, &argv, NULL);
fw_cfg = pc_fw_cfg_init();
s = qtest_init("-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8");
fw_cfg = pc_fw_cfg_init(s);
qtest_add_func("fw_cfg/signature", test_fw_cfg_signature);
qtest_add_func("fw_cfg/id", test_fw_cfg_id);
@ -125,15 +126,9 @@ int main(int argc, char **argv)
qtest_add_func("fw_cfg/numa", test_fw_cfg_numa);
qtest_add_func("fw_cfg/boot_menu", test_fw_cfg_boot_menu);
cmdline = g_strdup_printf("-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8 ");
s = qtest_start(cmdline);
g_free(cmdline);
ret = g_test_run();
if (s) {
qtest_quit(s);
}
qtest_quit(s);
return ret;
}

2
tests/i440fx-test.c
View File

@ -38,7 +38,7 @@ static QPCIBus *test_start_get_bus(const TestData *s)
cmdline = g_strdup_printf("-smp %d", s->num_cpus);
qtest_start(cmdline);
g_free(cmdline);
return qpci_init_pc(NULL);
return qpci_init_pc(global_qtest, NULL);
}
static void test_i440fx_defaults(gconstpointer opaque)

4
tests/ide-test.c
View File

@ -132,7 +132,7 @@ static void ide_test_start(const char *cmdline_fmt, ...)
va_end(ap);
qtest_start(cmdline);
guest_malloc = pc_alloc_init();
guest_malloc = pc_alloc_init(global_qtest);
g_free(cmdline);
}
@ -150,7 +150,7 @@ static QPCIDevice *get_pci_device(QPCIBar *bmdma_bar, QPCIBar *ide_bar)
uint16_t vendor_id, device_id;
if (!pcibus) {
pcibus = qpci_init_pc(NULL);
pcibus = qpci_init_pc(global_qtest, NULL);
}
/* Find PCI device and verify it's the right one */

1
tests/ivshmem-test.c
View File

@ -131,6 +131,7 @@ static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
g_printerr("ivshmem-test tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
global_qtest = s->qs->qts;
s->dev = get_device(s->qs->pcibus);
s->reg_bar = qpci_iomap(s->dev, 0, &barsize);

49
tests/libqos/ahci.c
View File

@ -123,13 +123,13 @@ bool is_atapi(AHCIQState *ahci, uint8_t port)
/**
* Locate, verify, and return a handle to the AHCI device.
*/
QPCIDevice *get_ahci_device(uint32_t *fingerprint)
QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint)
{
QPCIDevice *ahci;
uint32_t ahci_fingerprint;
QPCIBus *pcibus;
pcibus = qpci_init_pc(NULL);
pcibus = qpci_init_pc(qts, NULL);
/* Find the AHCI PCI device and verify it's the right one. */
ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
@ -283,7 +283,8 @@ void ahci_hba_enable(AHCIQState *ahci)
/* Allocate Memory for the Command List Buffer & FIS Buffer */
/* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20);
qtest_memset(ahci->parent->qts, ahci->port[i].clb, 0x00,
num_cmd_slots * 0x20);
g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
g_assert_cmphex(ahci->port[i].clb, ==,
@ -291,7 +292,7 @@ void ahci_hba_enable(AHCIQState *ahci)
/* PxFB space ... 0x100, as in 4.2.1 p 35 */
ahci->port[i].fb = ahci_alloc(ahci, 0x100);
qmemset(ahci->port[i].fb, 0x00, 0x100);
qtest_memset(ahci->parent->qts, ahci->port[i].fb, 0x00, 0x100);
g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
g_assert_cmphex(ahci->port[i].fb, ==,
@ -397,7 +398,7 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port)
g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
/* Wipe the FIS-Receive Buffer */
qmemset(ahci->port[port].fb, 0x00, 0x100);
qtest_memset(ahci->parent->qts, ahci->port[port].fb, 0x00, 0x100);
}
/**
@ -466,7 +467,7 @@ void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
RegD2HFIS *d2h = g_malloc0(0x20);
uint32_t reg;
memread(ahci->port[port].fb + 0x40, d2h, 0x20);
qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
g_assert_cmphex(d2h->fis_type, ==, 0x34);
reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
@ -484,7 +485,7 @@ void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
/* We cannot check the Status or E_Status registers, because
* the status may have again changed between the PIO Setup FIS
* and the conclusion of the command with the D2H Register FIS. */
memread(ahci->port[port].fb + 0x20, pio, 0x20);
qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x20, pio, 0x20);
g_assert_cmphex(pio->fis_type, ==, 0x5f);
/* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire
@ -516,7 +517,7 @@ void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
{
uint64_t ba = ahci->port[port].clb;
ba += slot * sizeof(AHCICommandHeader);
memread(ba, cmd, sizeof(AHCICommandHeader));
qtest_memread(ahci->parent->qts, ba, cmd, sizeof(AHCICommandHeader));
cmd->flags = le16_to_cpu(cmd->flags);
cmd->prdtl = le16_to_cpu(cmd->prdtl);
@ -537,7 +538,7 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
tmp.prdbc = cpu_to_le32(cmd->prdbc);
tmp.ctba = cpu_to_le64(cmd->ctba);
memwrite(ba, &tmp, sizeof(AHCICommandHeader));
qtest_memwrite(ahci->parent->qts, ba, &tmp, sizeof(AHCICommandHeader));
}
void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
@ -575,7 +576,7 @@ void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
tmp.count = cpu_to_le16(tmp.count);
}
memwrite(addr, &tmp, sizeof(tmp));
qtest_memwrite(ahci->parent->qts, addr, &tmp, sizeof(tmp));
}
unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
@ -636,7 +637,7 @@ void ahci_exec(AHCIQState *ahci, uint8_t port,
if (opts->size && !opts->buffer) {
opts->buffer = ahci_alloc(ahci, opts->size);
g_assert(opts->buffer);
qmemset(opts->buffer, 0x00, opts->size);
qtest_memset(ahci->parent->qts, opts->buffer, 0x00, opts->size);
}
/* Command creation */
@ -661,15 +662,15 @@ void ahci_exec(AHCIQState *ahci, uint8_t port,
ahci_command_commit(ahci, cmd, port);
ahci_command_issue_async(ahci, cmd);
if (opts->error) {
qmp_eventwait("STOP");
qtest_qmp_eventwait(ahci->parent->qts, "STOP");
}
if (opts->mid_cb) {
rc = opts->mid_cb(ahci, cmd, opts);
g_assert_cmpint(rc, ==, 0);
}
if (opts->error) {
qmp_async("{'execute':'cont' }");
qmp_eventwait("RESUME");
qtest_async_qmp(ahci->parent->qts, "{'execute':'cont' }");
qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
}
/* Wait for command to complete and verify sanity */
@ -697,7 +698,7 @@ AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
ahci_command_commit(ahci, cmd, port);
ahci_command_issue_async(ahci, cmd);
qmp_eventwait("STOP");
qtest_qmp_eventwait(ahci->parent->qts, "STOP");
return cmd;
}
@ -706,8 +707,8 @@ AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
{
/* Complete the command */
qmp_async("{'execute':'cont' }");
qmp_eventwait("RESUME");
qtest_async_qmp(ahci->parent->qts, "{'execute':'cont' }");
qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
ahci_command_wait(ahci, cmd);
ahci_command_verify(ahci, cmd);
ahci_command_free(cmd);
@ -754,16 +755,16 @@ void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
g_assert(props);
ptr = ahci_alloc(ahci, bufsize);
g_assert(!bufsize || ptr);
qmemset(ptr, 0x00, bufsize);
qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
if (bufsize && props->write) {
bufwrite(ptr, buffer, bufsize);
qtest_bufwrite(ahci->parent->qts, ptr, buffer, bufsize);
}
ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
if (bufsize && props->read) {
bufread(ptr, buffer, bufsize);
qtest_bufread(ahci->parent->qts, ptr, buffer, bufsize);
}
ahci_free(ahci, ptr);
@ -901,7 +902,7 @@ static int copy_buffer(AHCIQState *ahci, AHCICommand *cmd,
const AHCIOpts *opts)
{
unsigned char *rx = opts->opaque;
bufread(opts->buffer, rx, opts->size);
qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
return 0;
}
@ -1141,7 +1142,7 @@ void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
ahci_write_fis(ahci, cmd);
/* Then ATAPI CMD, if needed */
if (cmd->props->atapi) {
memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16);
qtest_memwrite(ahci->parent->qts, table_ptr + 0x40, cmd->atapi_cmd, 16);
}
/* Construct and write the PRDs to the command table */
@ -1162,8 +1163,8 @@ void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
/* Commit the PRD entry to the Command Table */
memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),
&prd, sizeof(PRD));
qtest_memwrite(ahci->parent->qts, table_ptr + 0x80 + (i * sizeof(PRD)),
&prd, sizeof(PRD));
}
/* Bookmark the PRDTL and CTBA values */

2
tests/libqos/ahci.h
View File

@ -571,7 +571,7 @@ void ahci_free(AHCIQState *ahci, uint64_t addr);
void ahci_clean_mem(AHCIQState *ahci);
/* Device management */
QPCIDevice *get_ahci_device(uint32_t *fingerprint);
QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint);
void free_ahci_device(QPCIDevice *dev);
void ahci_pci_enable(AHCIQState *ahci);
void start_ahci_device(AHCIQState *ahci);

14
tests/libqos/fw_cfg.c
View File

@ -56,7 +56,7 @@ uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key)
static void mm_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
{
writew(fw_cfg->base, key);
qtest_writew(fw_cfg->qts, fw_cfg->base, key);
}
static void mm_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
@ -65,15 +65,16 @@ static void mm_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
int i;
for (i = 0; i < len; i++) {
ptr[i] = readb(fw_cfg->base + 2);
ptr[i] = qtest_readb(fw_cfg->qts, fw_cfg->base + 2);
}
}
QFWCFG *mm_fw_cfg_init(uint64_t base)
QFWCFG *mm_fw_cfg_init(QTestState *qts, uint64_t base)
{
QFWCFG *fw_cfg = g_malloc0(sizeof(*fw_cfg));
fw_cfg->base = base;
fw_cfg->qts = qts;
fw_cfg->select = mm_fw_cfg_select;
fw_cfg->read = mm_fw_cfg_read;
@ -82,7 +83,7 @@ QFWCFG *mm_fw_cfg_init(uint64_t base)
static void io_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
{
outw(fw_cfg->base, key);
qtest_outw(fw_cfg->qts, fw_cfg->base, key);
}
static void io_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
@ -91,15 +92,16 @@ static void io_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
int i;
for (i = 0; i < len; i++) {
ptr[i] = inb(fw_cfg->base + 1);
ptr[i] = qtest_inb(fw_cfg->qts, fw_cfg->base + 1);
}
}
QFWCFG *io_fw_cfg_init(uint16_t base)
QFWCFG *io_fw_cfg_init(QTestState *qts, uint16_t base)
{
QFWCFG *fw_cfg = g_malloc0(sizeof(*fw_cfg));
fw_cfg->base = base;
fw_cfg->qts = qts;
fw_cfg->select = io_fw_cfg_select;
fw_cfg->read = io_fw_cfg_read;

10
tests/libqos/fw_cfg.h
View File

@ -13,12 +13,14 @@
#ifndef LIBQOS_FW_CFG_H
#define LIBQOS_FW_CFG_H
#include "libqtest.h"
typedef struct QFWCFG QFWCFG;
struct QFWCFG
{
uint64_t base;
QTestState *qts;
void (*select)(QFWCFG *fw_cfg, uint16_t key);
void (*read)(QFWCFG *fw_cfg, void *data, size_t len);
};
@ -30,12 +32,12 @@ uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key);
uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key);
uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key);
QFWCFG *mm_fw_cfg_init(uint64_t base);
QFWCFG *io_fw_cfg_init(uint16_t base);
QFWCFG *mm_fw_cfg_init(QTestState *qts, uint64_t base);
QFWCFG *io_fw_cfg_init(QTestState *qts, uint16_t base);
static inline QFWCFG *pc_fw_cfg_init(void)
static inline QFWCFG *pc_fw_cfg_init(QTestState *qts)
{
return io_fw_cfg_init(0x510);
return io_fw_cfg_init(qts, 0x510);
}
#endif

67
tests/libqos/i2c-imx.c
View File

@ -40,8 +40,8 @@ typedef struct IMXI2C {
static void imx_i2c_set_slave_addr(IMXI2C *s, uint8_t addr,
enum IMXI2CDirection direction)
{
writeb(s->addr + I2DR_ADDR, (addr << 1) |
(direction == IMX_I2C_READ ? 1 : 0));
qtest_writeb(s->parent.qts, s->addr + I2DR_ADDR,
(addr << 1) | (direction == IMX_I2C_READ ? 1 : 0));
}
static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,
@ -63,35 +63,35 @@ static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,
I2CR_MTX |
I2CR_TXAK;
writeb(s->addr + I2CR_ADDR, data);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) != 0);
/* set the slave address */
imx_i2c_set_slave_addr(s, addr, IMX_I2C_WRITE);
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) != 0);
g_assert((status & I2SR_RXAK) == 0);
/* ack the interrupt */
writeb(s->addr + I2SR_ADDR, 0);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) == 0);
while (size < len) {
/* check we are still busy */
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) != 0);
/* write the data */
writeb(s->addr + I2DR_ADDR, buf[size]);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2DR_ADDR, buf[size]);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) != 0);
g_assert((status & I2SR_RXAK) == 0);
/* ack the interrupt */
writeb(s->addr + I2SR_ADDR, 0);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) == 0);
size++;
@ -99,8 +99,8 @@ static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,
/* release the bus */
data &= ~(I2CR_MSTA | I2CR_MTX);
writeb(s->addr + I2CR_ADDR, data);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) == 0);
}
@ -123,19 +123,19 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,
I2CR_MTX |
I2CR_TXAK;
writeb(s->addr + I2CR_ADDR, data);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) != 0);
/* set the slave address */
imx_i2c_set_slave_addr(s, addr, IMX_I2C_READ);
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) != 0);
g_assert((status & I2SR_RXAK) == 0);
/* ack the interrupt */
writeb(s->addr + I2SR_ADDR, 0);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) == 0);
/* set the bus for read */
@ -144,23 +144,23 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,
if (len != 1) {
data &= ~I2CR_TXAK;
}
writeb(s->addr + I2CR_ADDR, data);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) != 0);
/* dummy read */
readb(s->addr + I2DR_ADDR);
status = readb(s->addr + I2SR_ADDR);
qtest_readb(i2c->qts, s->addr + I2DR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) != 0);
/* ack the interrupt */
writeb(s->addr + I2SR_ADDR, 0);
status = readb(s->addr + I2SR_ADDR);
qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) == 0);
while (size < len) {
/* check we are still busy */
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) != 0);
if (size == (len - 1)) {
@ -170,30 +170,30 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,
/* ack the data read */
data |= I2CR_TXAK;
}
writeb(s->addr + I2CR_ADDR, data);
qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);
/* read the data */
buf[size] = readb(s->addr + I2DR_ADDR);
buf[size] = qtest_readb(i2c->qts, s->addr + I2DR_ADDR);
if (size != (len - 1)) {
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) != 0);
/* ack the interrupt */
writeb(s->addr + I2SR_ADDR, 0);
qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);
}
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IIF) == 0);
size++;
}
status = readb(s->addr + I2SR_ADDR);
status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
g_assert((status & I2SR_IBB) == 0);
}
I2CAdapter *imx_i2c_create(uint64_t addr)
I2CAdapter *imx_i2c_create(QTestState *qts, uint64_t addr)
{
IMXI2C *s = g_malloc0(sizeof(*s));
I2CAdapter *i2c = (I2CAdapter *)s;
@ -202,6 +202,7 @@ I2CAdapter *imx_i2c_create(uint64_t addr)
i2c->send = imx_i2c_send;
i2c->recv = imx_i2c_recv;
i2c->qts = qts;
return i2c;
}

45
tests/libqos/i2c-omap.c
View File

@ -51,8 +51,8 @@ static void omap_i2c_set_slave_addr(OMAPI2C *s, uint8_t addr)
{
uint16_t data = addr;
writew(s->addr + OMAP_I2C_SA, data);
data = readw(s->addr + OMAP_I2C_SA);
qtest_writew(s->parent.qts, s->addr + OMAP_I2C_SA, data);
data = qtest_readw(s->parent.qts, s->addr + OMAP_I2C_SA);
g_assert_cmphex(data, ==, addr);
}
@ -65,38 +65,38 @@ static void omap_i2c_send(I2CAdapter *i2c, uint8_t addr,
omap_i2c_set_slave_addr(s, addr);
data = len;
writew(s->addr + OMAP_I2C_CNT, data);
qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);
data = OMAP_I2C_CON_I2C_EN |
OMAP_I2C_CON_TRX |
OMAP_I2C_CON_MST |
OMAP_I2C_CON_STT |
OMAP_I2C_CON_STP;
writew(s->addr + OMAP_I2C_CON, data);
data = readw(s->addr + OMAP_I2C_CON);
qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);
g_assert((data & OMAP_I2C_CON_STP) != 0);
data = readw(s->addr + OMAP_I2C_STAT);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);
g_assert((data & OMAP_I2C_STAT_NACK) == 0);
while (len > 1) {
data = readw(s->addr + OMAP_I2C_STAT);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);
g_assert((data & OMAP_I2C_STAT_XRDY) != 0);
data = buf[0] | ((uint16_t)buf[1] << 8);
writew(s->addr + OMAP_I2C_DATA, data);
qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);
buf = (uint8_t *)buf + 2;
len -= 2;
}
if (len == 1) {
data = readw(s->addr + OMAP_I2C_STAT);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);
g_assert((data & OMAP_I2C_STAT_XRDY) != 0);
data = buf[0];
writew(s->addr + OMAP_I2C_DATA, data);
qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);
}
data = readw(s->addr + OMAP_I2C_CON);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);
g_assert((data & OMAP_I2C_CON_STP) == 0);
}
@ -109,30 +109,30 @@ static void omap_i2c_recv(I2CAdapter *i2c, uint8_t addr,
omap_i2c_set_slave_addr(s, addr);
data = len;
writew(s->addr + OMAP_I2C_CNT, data);
qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);
data = OMAP_I2C_CON_I2C_EN |
OMAP_I2C_CON_MST |
OMAP_I2C_CON_STT |
OMAP_I2C_CON_STP;
writew(s->addr + OMAP_I2C_CON, data);
data = readw(s->addr + OMAP_I2C_CON);
qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);
g_assert((data & OMAP_I2C_CON_STP) == 0);
data = readw(s->addr + OMAP_I2C_STAT);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);
g_assert((data & OMAP_I2C_STAT_NACK) == 0);
data = readw(s->addr + OMAP_I2C_CNT);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CNT);
g_assert_cmpuint(data, ==, len);
while (len > 0) {
data = readw(s->addr + OMAP_I2C_STAT);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);
g_assert((data & OMAP_I2C_STAT_RRDY) != 0);
g_assert((data & OMAP_I2C_STAT_ROVR) == 0);
data = readw(s->addr + OMAP_I2C_DATA);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_DATA);
stat = readw(s->addr + OMAP_I2C_STAT);
stat = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);
if (unlikely(len == 1)) {
g_assert((stat & OMAP_I2C_STAT_SBD) != 0);
@ -148,11 +148,11 @@ static void omap_i2c_recv(I2CAdapter *i2c, uint8_t addr,
}
}
data = readw(s->addr + OMAP_I2C_CON);
data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);
g_assert((data & OMAP_I2C_CON_STP) == 0);
}
I2CAdapter *omap_i2c_create(uint64_t addr)
I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr)
{
OMAPI2C *s = g_malloc0(sizeof(*s));
I2CAdapter *i2c = (I2CAdapter *)s;
@ -162,9 +162,10 @@ I2CAdapter *omap_i2c_create(uint64_t addr)
i2c->send = omap_i2c_send;
i2c->recv = omap_i2c_recv;
i2c->qts = qts;
/* verify the mmio address by looking for a known signature */
data = readw(addr + OMAP_I2C_REV);
data = qtest_readw(qts, addr + OMAP_I2C_REV);
g_assert_cmphex(data, ==, 0x34);
return i2c;

7
tests/libqos/i2c.h
View File

@ -9,6 +9,7 @@
#ifndef LIBQOS_I2C_H
#define LIBQOS_I2C_H
#include "libqtest.h"
typedef struct I2CAdapter I2CAdapter;
struct I2CAdapter {
@ -16,6 +17,8 @@ struct I2CAdapter {
const uint8_t *buf, uint16_t len);
void (*recv)(I2CAdapter *adapter, uint8_t addr,
uint8_t *buf, uint16_t len);
QTestState *qts;
};
void i2c_send(I2CAdapter *i2c, uint8_t addr,
@ -24,9 +27,9 @@ void i2c_recv(I2CAdapter *i2c, uint8_t addr,
uint8_t *buf, uint16_t len);
/* libi2c-omap.c */
I2CAdapter *omap_i2c_create(uint64_t addr);
I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr);
/* libi2c-imx.c */
I2CAdapter *imx_i2c_create(uint64_t addr);
I2CAdapter *imx_i2c_create(QTestState *qts, uint64_t addr);
#endif

2
tests/libqos/libqos-pc.c
View File

@ -25,7 +25,7 @@ QOSState *qtest_pc_boot(const char *cmdline_fmt, ...)
qs = qtest_vboot(&qos_ops, cmdline_fmt, ap);
va_end(ap);
qtest_irq_intercept_in(global_qtest, "ioapic");
qtest_irq_intercept_in(qs->qts, "ioapic");
return qs;
}

40
tests/libqos/libqos.c
View File

@ -18,18 +18,14 @@ QOSState *qtest_vboot(QOSOps *ops, const char *cmdline_fmt, va_list ap)
{
char *cmdline;
struct QOSState *qs = g_new(QOSState, 1);
QOSState *qs = g_new0(QOSState, 1);
cmdline = g_strdup_vprintf(cmdline_fmt, ap);
qs->qts = qtest_start(cmdline);
qs->qts = qtest_init(cmdline);
qs->ops = ops;
if (ops) {
if (ops->init_allocator) {
qs->alloc = ops->init_allocator(ALLOC_NO_FLAGS);
}
if (ops->qpci_init && qs->alloc) {
qs->pcibus = ops->qpci_init(qs->alloc);
}
qs->alloc = ops->init_allocator(qs->qts, ALLOC_NO_FLAGS);
qs->pcibus = ops->qpci_init(qs->qts, qs->alloc);
}
g_free(cmdline);
@ -85,29 +81,21 @@ void set_context(QOSState *s)
global_qtest = s->qts;
}
static QDict *qmp_execute(const char *command)
static QDict *qmp_execute(QTestState *qts, const char *command)
{
char *fmt;
QDict *rsp;
fmt = g_strdup_printf("{ 'execute': '%s' }", command);
rsp = qmp(fmt);
g_free(fmt);
return rsp;
return qtest_qmp(qts, "{ 'execute': %s }", command);
}
void migrate(QOSState *from, QOSState *to, const char *uri)
{
const char *st;
char *s;
QDict *rsp, *sub;
bool running;
set_context(from);
/* Is the machine currently running? */
rsp = qmp_execute("query-status");
rsp = qmp_execute(from->qts, "query-status");
g_assert(qdict_haskey(rsp, "return"));
sub = qdict_get_qdict(rsp, "return");
g_assert(qdict_haskey(sub, "running"));
@ -115,30 +103,28 @@ void migrate(QOSState *from, QOSState *to, const char *uri)
QDECREF(rsp);
/* Issue the migrate command. */
s = g_strdup_printf("{ 'execute': 'migrate',"
"'arguments': { 'uri': '%s' } }",
uri);
rsp = qmp(s);
g_free(s);
rsp = qtest_qmp(from->qts,
"{ 'execute': 'migrate', 'arguments': { 'uri': %s }}",
uri);
g_assert(qdict_haskey(rsp, "return"));
QDECREF(rsp);
/* Wait for STOP event, but only if we were running: */
if (running) {
qmp_eventwait("STOP");
qtest_qmp_eventwait(from->qts, "STOP");
}
/* If we were running, we can wait for an event. */
if (running) {
migrate_allocator(from->alloc, to->alloc);
set_context(to);
qmp_eventwait("RESUME");
qtest_qmp_eventwait(to->qts, "RESUME");
return;
}
/* Otherwise, we need to wait: poll until migration is completed. */
while (1) {
rsp = qmp_execute("query-migrate");
rsp = qmp_execute(from->qts, "query-migrate");
g_assert(qdict_haskey(rsp, "return"));
sub = qdict_get_qdict(rsp, "return");
g_assert(qdict_haskey(sub, "status"));

4
tests/libqos/libqos.h
View File

@ -8,9 +8,9 @@
typedef struct QOSState QOSState;
typedef struct QOSOps {
QGuestAllocator *(*init_allocator)(QAllocOpts);
QGuestAllocator *(*init_allocator)(QTestState *qts, QAllocOpts);
void (*uninit_allocator)(QGuestAllocator *);
QPCIBus *(*qpci_init)(QGuestAllocator *alloc);
QPCIBus *(*qpci_init)(QTestState *qts, QGuestAllocator *alloc);
void (*qpci_free)(QPCIBus *bus);
void (*shutdown)(QOSState *);
} QOSOps;

8
tests/libqos/malloc-pc.c
View File

@ -29,11 +29,11 @@ void pc_alloc_uninit(QGuestAllocator *allocator)
alloc_uninit(allocator);
}
QGuestAllocator *pc_alloc_init_flags(QAllocOpts flags)
QGuestAllocator *pc_alloc_init_flags(QTestState *qts, QAllocOpts flags)
{
QGuestAllocator *s;
uint64_t ram_size;
QFWCFG *fw_cfg = pc_fw_cfg_init();
QFWCFG *fw_cfg = pc_fw_cfg_init(qts);
ram_size = qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE);
s = alloc_init_flags(flags, 1 << 20, MIN(ram_size, 0xE0000000));
@ -45,7 +45,7 @@ QGuestAllocator *pc_alloc_init_flags(QAllocOpts flags)
return s;
}
inline QGuestAllocator *pc_alloc_init(void)
inline QGuestAllocator *pc_alloc_init(QTestState *qts)
{
return pc_alloc_init_flags(ALLOC_NO_FLAGS);
return pc_alloc_init_flags(qts, ALLOC_NO_FLAGS);
}

4
tests/libqos/malloc-pc.h
View File

@ -15,8 +15,8 @@
#include "libqos/malloc.h"
QGuestAllocator *pc_alloc_init(void);
QGuestAllocator *pc_alloc_init_flags(QAllocOpts flags);
QGuestAllocator *pc_alloc_init(QTestState *qts);
QGuestAllocator *pc_alloc_init_flags(QTestState *qts, QAllocOpts flags);
void pc_alloc_uninit(QGuestAllocator *allocator);
#endif

4
tests/libqos/malloc-spapr.c
View File

@ -22,7 +22,7 @@ void spapr_alloc_uninit(QGuestAllocator *allocator)
alloc_uninit(allocator);
}
QGuestAllocator *spapr_alloc_init_flags(QAllocOpts flags)
QGuestAllocator *spapr_alloc_init_flags(QTestState *qts, QAllocOpts flags)
{
QGuestAllocator *s;
@ -34,5 +34,5 @@ QGuestAllocator *spapr_alloc_init_flags(QAllocOpts flags)
QGuestAllocator *spapr_alloc_init(void)
{
return spapr_alloc_init_flags(ALLOC_NO_FLAGS);
return spapr_alloc_init_flags(NULL, ALLOC_NO_FLAGS);
}

2
tests/libqos/malloc-spapr.h
View File

@ -11,7 +11,7 @@
#include "libqos/malloc.h"
QGuestAllocator *spapr_alloc_init(void);
QGuestAllocator *spapr_alloc_init_flags(QAllocOpts flags);
QGuestAllocator *spapr_alloc_init_flags(QTestState *qts, QAllocOpts flags);
void spapr_alloc_uninit(QGuestAllocator *allocator);
#endif

1
tests/libqos/malloc.h
View File

@ -14,6 +14,7 @@
#define LIBQOS_MALLOC_H
#include "qemu/queue.h"
#include "libqtest.h"
typedef enum {
ALLOC_NO_FLAGS = 0x00,

13
tests/libqos/pci-pc.c
View File

@ -115,11 +115,11 @@ static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint3
outl(0xcfc, value);
}
QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
QPCIBus *qpci_init_pc(QTestState *qts, QGuestAllocator *alloc)
{
QPCIBusPC *ret;
QPCIBusPC *ret = g_new0(QPCIBusPC, 1);
ret = g_malloc(sizeof(*ret));
assert(qts);
ret->bus.pio_readb = qpci_pc_pio_readb;
ret->bus.pio_readw = qpci_pc_pio_readw;
@ -142,6 +142,7 @@ QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
ret->bus.config_writew = qpci_pc_config_writew;
ret->bus.config_writel = qpci_pc_config_writel;
ret->bus.qts = qts;
ret->bus.pio_alloc_ptr = 0xc000;
ret->bus.mmio_alloc_ptr = 0xE0000000;
ret->bus.mmio_limit = 0x100000000ULL;
@ -173,9 +174,5 @@ void qpci_unplug_acpi_device_test(const char *id, uint8_t slot)
outb(ACPI_PCIHP_ADDR + PCI_EJ_BASE, 1 << slot);
response = qmp("");
g_assert(response);
g_assert(qdict_haskey(response, "event"));
g_assert(!strcmp(qdict_get_str(response, "event"), "DEVICE_DELETED"));
QDECREF(response);
qmp_eventwait("DEVICE_DELETED");
}

2
tests/libqos/pci-pc.h
View File

@ -16,7 +16,7 @@
#include "libqos/pci.h"
#include "libqos/malloc.h"
QPCIBus *qpci_init_pc(QGuestAllocator *alloc);
QPCIBus *qpci_init_pc(QTestState *qts, QGuestAllocator *alloc);
void qpci_free_pc(QPCIBus *bus);
#endif

25
tests/libqos/pci-spapr.c
View File

@ -108,21 +108,24 @@ static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
uint32_t config_addr = (devfn << 8) | offset;
return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 1);
return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid,
config_addr, 1);
}
static uint16_t qpci_spapr_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
uint32_t config_addr = (devfn << 8) | offset;
return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 2);
return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid,
config_addr, 2);
}
static uint32_t qpci_spapr_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
uint32_t config_addr = (devfn << 8) | offset;
return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 4);
return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid,
config_addr, 4);
}
static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset,
@ -130,7 +133,8 @@ static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset,
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
uint32_t config_addr = (devfn << 8) | offset;
qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 1, value);
qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid,
config_addr, 1, value);
}
static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset,
@ -138,7 +142,8 @@ static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset,
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
uint32_t config_addr = (devfn << 8) | offset;
qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 2, value);
qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid,
config_addr, 2, value);
}
static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
@ -146,7 +151,8 @@ static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
uint32_t config_addr = (devfn << 8) | offset;
qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 4, value);
qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid,
config_addr, 4, value);
}
#define SPAPR_PCI_BASE (1ULL << 45)
@ -154,11 +160,11 @@ static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
#define SPAPR_PCI_MMIO32_WIN_SIZE 0x80000000 /* 2 GiB */
#define SPAPR_PCI_IO_WIN_SIZE 0x10000
QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
QPCIBus *qpci_init_spapr(QTestState *qts, QGuestAllocator *alloc)
{
QPCIBusSPAPR *ret;
QPCIBusSPAPR *ret = g_new0(QPCIBusSPAPR, 1);
ret = g_malloc(sizeof(*ret));
assert(qts);
ret->alloc = alloc;
@ -197,6 +203,7 @@ QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
ret->mmio32.pci_base = SPAPR_PCI_MMIO32_WIN_SIZE;
ret->mmio32.size = SPAPR_PCI_MMIO32_WIN_SIZE;
ret->bus.qts = qts;
ret->bus.pio_alloc_ptr = 0xc000;
ret->bus.mmio_alloc_ptr = ret->mmio32.pci_base;
ret->bus.mmio_limit = ret->mmio32.pci_base + ret->mmio32.size;

2
tests/libqos/pci-spapr.h
View File

@ -11,7 +11,7 @@
#include "libqos/malloc.h"
#include "libqos/pci.h"
QPCIBus *qpci_init_spapr(QGuestAllocator *alloc);
QPCIBus *qpci_init_spapr(QTestState *qts, QGuestAllocator *alloc);
void qpci_free_spapr(QPCIBus *bus);
#endif

1
tests/libqos/pci.h
View File

@ -48,6 +48,7 @@ struct QPCIBus {
void (*config_writel)(QPCIBus *bus, int devfn,
uint8_t offset, uint32_t value);
QTestState *qts;
uint16_t pio_alloc_ptr;
uint64_t mmio_alloc_ptr, mmio_limit;
};

36
tests/libqos/rtas.c
View File

@ -7,26 +7,28 @@
#include "libqtest.h"
#include "libqos/rtas.h"
static void qrtas_copy_args(uint64_t target_args, uint32_t nargs,
uint32_t *args)
static void qrtas_copy_args(QTestState *qts, uint64_t target_args,
uint32_t nargs, uint32_t *args)
{
int i;
for (i = 0; i < nargs; i++) {
writel(target_args + i * sizeof(uint32_t), args[i]);
qtest_writel(qts, target_args + i * sizeof(uint32_t), args[i]);
}
}
static void qrtas_copy_ret(uint64_t target_ret, uint32_t nret, uint32_t *ret)
static void qrtas_copy_ret(QTestState *qts, uint64_t target_ret,
uint32_t nret, uint32_t *ret)
{
int i;
for (i = 0; i < nret; i++) {
ret[i] = readl(target_ret + i * sizeof(uint32_t));
ret[i] = qtest_readl(qts, target_ret + i * sizeof(uint32_t));
}
}
static uint64_t qrtas_call(QGuestAllocator *alloc, const char *name,
static uint64_t qrtas_call(QTestState *qts, QGuestAllocator *alloc,
const char *name,
uint32_t nargs, uint32_t *args,
uint32_t nret, uint32_t *ret)
{
@ -36,10 +38,9 @@ static uint64_t qrtas_call(QGuestAllocator *alloc, const char *name,
target_args = guest_alloc(alloc, nargs * sizeof(uint32_t));
target_ret = guest_alloc(alloc, nret * sizeof(uint32_t));
qrtas_copy_args(target_args, nargs, args);
res = qtest_rtas_call(global_qtest, name,
nargs, target_args, nret, target_ret);
qrtas_copy_ret(target_ret, nret, ret);
qrtas_copy_args(qts, target_args, nargs, args);
res = qtest_rtas_call(qts, name, nargs, target_args, nret, target_ret);
qrtas_copy_ret(qts, target_ret, nret, ret);
guest_free(alloc, target_ret);
guest_free(alloc, target_args);
@ -47,12 +48,13 @@ static uint64_t qrtas_call(QGuestAllocator *alloc, const char *name,
return res;
}
int qrtas_get_time_of_day(QGuestAllocator *alloc, struct tm *tm, uint32_t *ns)
int qrtas_get_time_of_day(QTestState *qts, QGuestAllocator *alloc,
struct tm *tm, uint32_t *ns)
{
int res;
uint32_t ret[8];
res = qrtas_call(alloc, "get-time-of-day", 0, NULL, 8, ret);
res = qrtas_call(qts, alloc, "get-time-of-day", 0, NULL, 8, ret);
if (res != 0) {
return res;
}
@ -70,7 +72,8 @@ int qrtas_get_time_of_day(QGuestAllocator *alloc, struct tm *tm, uint32_t *ns)
return res;
}
uint32_t qrtas_ibm_read_pci_config(QGuestAllocator *alloc, uint64_t buid,
uint32_t qrtas_ibm_read_pci_config(QTestState *qts, QGuestAllocator *alloc,
uint64_t buid,
uint32_t addr, uint32_t size)
{
int res;
@ -80,7 +83,7 @@ uint32_t qrtas_ibm_read_pci_config(QGuestAllocator *alloc, uint64_t buid,
args[1] = buid >> 32;
args[2] = buid & 0xffffffff;
args[3] = size;
res = qrtas_call(alloc, "ibm,read-pci-config", 4, args, 2, ret);
res = qrtas_call(qts, alloc, "ibm,read-pci-config", 4, args, 2, ret);
if (res != 0) {
return -1;
}
@ -92,7 +95,8 @@ uint32_t qrtas_ibm_read_pci_config(QGuestAllocator *alloc, uint64_t buid,
return ret[1];
}
int qrtas_ibm_write_pci_config(QGuestAllocator *alloc, uint64_t buid,
int qrtas_ibm_write_pci_config(QTestState *qts, QGuestAllocator *alloc,
uint64_t buid,
uint32_t addr, uint32_t size, uint32_t val)
{
int res;
@ -103,7 +107,7 @@ int qrtas_ibm_write_pci_config(QGuestAllocator *alloc, uint64_t buid,
args[2] = buid & 0xffffffff;
args[3] = size;
args[4] = val;
res = qrtas_call(alloc, "ibm,write-pci-config", 5, args, 1, ret);
res = qrtas_call(qts, alloc, "ibm,write-pci-config", 5, args, 1, ret);
if (res != 0) {
return -1;
}

12
tests/libqos/rtas.h
View File

@ -7,9 +7,11 @@
#define LIBQOS_RTAS_H
#include "libqos/malloc.h"
int qrtas_get_time_of_day(QGuestAllocator *alloc, struct tm *tm, uint32_t *ns);
uint32_t qrtas_ibm_read_pci_config(QGuestAllocator *alloc, uint64_t buid,
uint32_t addr, uint32_t size);
int qrtas_ibm_write_pci_config(QGuestAllocator *alloc, uint64_t buid,
uint32_t addr, uint32_t size, uint32_t val);
int qrtas_get_time_of_day(QTestState *qts, QGuestAllocator *alloc,
struct tm *tm, uint32_t *ns);
uint32_t qrtas_ibm_read_pci_config(QTestState *qts, QGuestAllocator *alloc,
uint64_t buid, uint32_t addr, uint32_t size);
int qrtas_ibm_write_pci_config(QTestState *qts, QGuestAllocator *alloc,
uint64_t buid, uint32_t addr, uint32_t size,
uint32_t val);
#endif /* LIBQOS_RTAS_H */

19
tests/libqtest.c
View File

@ -15,12 +15,13 @@
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include <sys/socket.h>
#include <sys/wait.h>
#include <sys/un.h>
#include "libqtest.h"
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qapi/qmp/json-parser.h"
#include "qapi/qmp/json-streamer.h"
@ -363,12 +364,14 @@ redo:
g_string_free(line, TRUE);
if (strcmp(words[0], "IRQ") == 0) {
int irq;
long irq;
int ret;
g_assert(words[1] != NULL);
g_assert(words[2] != NULL);
irq = strtoul(words[2], NULL, 0);
ret = qemu_strtol(words[2], NULL, 0, &irq);
g_assert(!ret);
g_assert_cmpint(irq, >=, 0);
g_assert_cmpint(irq, <, MAX_IRQ);
@ -730,11 +733,13 @@ void qtest_outl(QTestState *s, uint16_t addr, uint32_t value)
static uint32_t qtest_in(QTestState *s, const char *cmd, uint16_t addr)
{
gchar **args;
uint32_t value;
int ret;
unsigned long value;
qtest_sendf(s, "%s 0x%x\n", cmd, addr);
args = qtest_rsp(s, 2);
value = strtoul(args[1], NULL, 0);
ret = qemu_strtoul(args[1], NULL, 0, &value);
g_assert(!ret && value <= UINT32_MAX);
g_strfreev(args);
return value;
@ -785,11 +790,13 @@ void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value)
static uint64_t qtest_read(QTestState *s, const char *cmd, uint64_t addr)
{
gchar **args;
int ret;
uint64_t value;
qtest_sendf(s, "%s 0x%" PRIx64 "\n", cmd, addr);
args = qtest_rsp(s, 2);
value = strtoull(args[1], NULL, 0);
ret = qemu_strtou64(args[1], NULL, 0, &value);
g_assert(!ret);
g_strfreev(args);
return value;

123
tests/m48t59-test.c
View File

@ -28,47 +28,48 @@
static uint32_t base;
static uint16_t reg_base = 0x1ff0; /* 0x7f0 for m48t02 */
static int base_year;
static const char *base_machine;
static bool use_mmio;
static uint8_t cmos_read_mmio(uint8_t reg)
static uint8_t cmos_read_mmio(QTestState *s, uint8_t reg)
{
return readb(base + (uint32_t)reg_base + (uint32_t)reg);
return qtest_readb(s, base + (uint32_t)reg_base + (uint32_t)reg);
}
static void cmos_write_mmio(uint8_t reg, uint8_t val)
static void cmos_write_mmio(QTestState *s, uint8_t reg, uint8_t val)
{
uint8_t data = val;
writeb(base + (uint32_t)reg_base + (uint32_t)reg, data);
qtest_writeb(s, base + (uint32_t)reg_base + (uint32_t)reg, data);
}
static uint8_t cmos_read_ioio(uint8_t reg)
static uint8_t cmos_read_ioio(QTestState *s, uint8_t reg)
{
outw(base + 0, reg_base + (uint16_t)reg);
return inb(base + 3);
qtest_outw(s, base + 0, reg_base + (uint16_t)reg);
return qtest_inb(s, base + 3);
}
static void cmos_write_ioio(uint8_t reg, uint8_t val)
static void cmos_write_ioio(QTestState *s, uint8_t reg, uint8_t val)
{
outw(base + 0, reg_base + (uint16_t)reg);
outb(base + 3, val);
qtest_outw(s, base + 0, reg_base + (uint16_t)reg);
qtest_outb(s, base + 3, val);
}
static uint8_t cmos_read(uint8_t reg)
static uint8_t cmos_read(QTestState *s, uint8_t reg)
{
if (use_mmio) {
return cmos_read_mmio(reg);
return cmos_read_mmio(s, reg);
} else {
return cmos_read_ioio(reg);
return cmos_read_ioio(s, reg);
}
}
static void cmos_write(uint8_t reg, uint8_t val)
static void cmos_write(QTestState *s, uint8_t reg, uint8_t val)
{
if (use_mmio) {
cmos_write_mmio(reg, val);
cmos_write_mmio(s, reg, val);
} else {
cmos_write_ioio(reg, val);
cmos_write_ioio(s, reg, val);
}
}
@ -106,18 +107,18 @@ static void print_tm(struct tm *tm)
}
#endif
static void cmos_get_date_time(struct tm *date)
static void cmos_get_date_time(QTestState *s, struct tm *date)
{
int sec, min, hour, mday, mon, year;
time_t ts;
struct tm dummy;
sec = cmos_read(RTC_SECONDS);
min = cmos_read(RTC_MINUTES);
hour = cmos_read(RTC_HOURS);
mday = cmos_read(RTC_DAY_OF_MONTH);
mon = cmos_read(RTC_MONTH);
year = cmos_read(RTC_YEAR);
sec = cmos_read(s, RTC_SECONDS);
min = cmos_read(s, RTC_MINUTES);
hour = cmos_read(s, RTC_HOURS);
mday = cmos_read(s, RTC_DAY_OF_MONTH);
mon = cmos_read(s, RTC_MONTH);
year = cmos_read(s, RTC_YEAR);
sec = bcd2dec(sec);
min = bcd2dec(min);
@ -143,11 +144,18 @@ static void cmos_get_date_time(struct tm *date)
ts = mktime(date);
}
static void check_time(int wiggle)
static QTestState *m48t59_qtest_start(void)
{
return qtest_startf("-M %s -rtc clock=vm", base_machine);
}
static void bcd_check_time(void)
{
struct tm start, date[4], end;
struct tm *datep;
time_t ts;
const int wiggle = 2;
QTestState *s = m48t59_qtest_start();
/*
* This check assumes a few things. First, we cannot guarantee that we get
@ -165,10 +173,10 @@ static void check_time(int wiggle)
ts = time(NULL);
gmtime_r(&ts, &start);
cmos_get_date_time(&date[0]);
cmos_get_date_time(&date[1]);
cmos_get_date_time(&date[2]);
cmos_get_date_time(&date[3]);
cmos_get_date_time(s, &date[0]);
cmos_get_date_time(s, &date[1]);
cmos_get_date_time(s, &date[2]);
cmos_get_date_time(s, &date[3]);
ts = time(NULL);
gmtime_r(&ts, &end);
@ -198,30 +206,15 @@ static void check_time(int wiggle)
g_assert_cmpint(ABS(t - s), <=, wiggle);
}
}
static int wiggle = 2;
static void bcd_check_time(void)
{
if (strcmp(qtest_get_arch(), "sparc64") == 0) {
base = 0x74;
base_year = 1900;
use_mmio = false;
} else if (strcmp(qtest_get_arch(), "sparc") == 0) {
base = 0x71200000;
base_year = 1968;
use_mmio = true;
} else { /* PPC: need to map macio in PCI */
g_assert_not_reached();
}
check_time(wiggle);
qtest_quit(s);
}
/* success if no crash or abort */
static void fuzz_registers(void)
{
unsigned int i;
QTestState *s = m48t59_qtest_start();
for (i = 0; i < 1000; i++) {
uint8_t reg, val;
@ -234,27 +227,47 @@ static void fuzz_registers(void)
continue;
}
cmos_write(reg, val);
cmos_read(reg);
cmos_write(s, reg, val);
cmos_read(s, reg);
}
qtest_quit(s);
}
static void base_setup(void)
{
const char *arch = qtest_get_arch();
if (g_str_equal(arch, "sparc")) {
/* Note: For sparc64, we'd need to map-in the PCI bridge memory first */
base = 0x71200000;
base_year = 1968;
base_machine = "SS-5";
use_mmio = true;
} else if (g_str_equal(arch, "ppc") || g_str_equal(arch, "ppc64")) {
base = 0xF0000000;
base_year = 1968;
base_machine = "ref405ep";
use_mmio = true;
} else {
g_assert_not_reached();
}
}
int main(int argc, char **argv)
{
QTestState *s = NULL;
int ret;
base_setup();
g_test_init(&argc, &argv, NULL);
s = qtest_start("-rtc clock=vm");
qtest_add_func("/rtc/bcd/check-time", bcd_check_time);
if (g_test_slow()) {
/* Do not run this in timing-sensitive environments */
qtest_add_func("/rtc/bcd-check-time", bcd_check_time);
}
qtest_add_func("/rtc/fuzz-registers", fuzz_registers);
ret = g_test_run();
if (s) {
qtest_quit(s);
}
return ret;
}

5
tests/megasas-test.c
View File

@ -15,13 +15,16 @@
static QOSState *qmegasas_start(const char *extra_opts)
{
QOSState *qs;
const char *arch = qtest_get_arch();
const char *cmd = "-drive id=hd0,if=none,file=null-co://,format=raw "
"-device megasas,id=scsi0,addr=04.0 "
"-device scsi-hd,bus=scsi0.0,drive=hd0 %s";
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
return qtest_pc_boot(cmd, extra_opts ? : "");
qs = qtest_pc_boot(cmd, extra_opts ? : "");
global_qtest = qs->qts;
return qs;
}
g_printerr("virtio-scsi tests are only available on x86 or ppc64\n");

2
tests/pxe-test.c
View File

@ -71,7 +71,7 @@ static void test_pxe_one(const testdef_t *test, bool ipv6)
test->model);
qtest_start(args);
boot_sector_test();
boot_sector_test(global_qtest);
qtest_quit(global_qtest);
g_free(args);
}

4
tests/q35-test.c
View File

@ -87,7 +87,7 @@ static void test_smram_lock(void)
qtest_start("-M q35");
pcibus = qpci_init_pc(NULL);
pcibus = qpci_init_pc(global_qtest, NULL);
g_assert(pcibus != NULL);
pcidev = qpci_device_find(pcibus, 0);
@ -146,7 +146,7 @@ static void test_tseg_size(const void *data)
g_free(cmdline);
/* locate the DRAM controller */
pcibus = qpci_init_pc(NULL);
pcibus = qpci_init_pc(global_qtest, NULL);
g_assert(pcibus != NULL);
pcidev = qpci_device_find(pcibus, 0);
g_assert(pcidev != NULL);

35
tests/qmp-test.c
View File

@ -43,32 +43,32 @@ static void test_version(QObject *version)
visit_free(v);
}
static void test_malformed(void)
static void test_malformed(QTestState *qts)
{
QDict *resp;
/* Not even a dictionary */
resp = qmp("null");
resp = qtest_qmp(qts, "null");
g_assert_cmpstr(get_error_class(resp), ==, "GenericError");
QDECREF(resp);
/* No "execute" key */
resp = qmp("{}");
resp = qtest_qmp(qts, "{}");
g_assert_cmpstr(get_error_class(resp), ==, "GenericError");
QDECREF(resp);
/* "execute" isn't a string */
resp = qmp("{ 'execute': true }");
resp = qtest_qmp(qts, "{ 'execute': true }");
g_assert_cmpstr(get_error_class(resp), ==, "GenericError");
QDECREF(resp);
/* "arguments" isn't a dictionary */
resp = qmp("{ 'execute': 'no-such-cmd', 'arguments': [] }");
resp = qtest_qmp(qts, "{ 'execute': 'no-such-cmd', 'arguments': [] }");
g_assert_cmpstr(get_error_class(resp), ==, "GenericError");
QDECREF(resp);
/* extra key */
resp = qmp("{ 'execute': 'no-such-cmd', 'extra': true }");
resp = qtest_qmp(qts, "{ 'execute': 'no-such-cmd', 'extra': true }");
g_assert_cmpstr(get_error_class(resp), ==, "GenericError");
QDECREF(resp);
}
@ -77,11 +77,12 @@ static void test_qmp_protocol(void)
{
QDict *resp, *q, *ret;
QList *capabilities;
QTestState *qts;
global_qtest = qtest_init_without_qmp_handshake(common_args);
qts = qtest_init_without_qmp_handshake(common_args);
/* Test greeting */
resp = qmp_receive();
resp = qtest_qmp_receive(qts);
q = qdict_get_qdict(resp, "QMP");
g_assert(q);
test_version(qdict_get(q, "version"));
@ -90,46 +91,46 @@ static void test_qmp_protocol(void)
QDECREF(resp);
/* Test valid command before handshake */
resp = qmp("{ 'execute': 'query-version' }");
resp = qtest_qmp(qts, "{ 'execute': 'query-version' }");
g_assert_cmpstr(get_error_class(resp), ==, "CommandNotFound");
QDECREF(resp);
/* Test malformed commands before handshake */
test_malformed();
test_malformed(qts);
/* Test handshake */
resp = qmp("{ 'execute': 'qmp_capabilities' }");
resp = qtest_qmp(qts, "{ 'execute': 'qmp_capabilities' }");
ret = qdict_get_qdict(resp, "return");
g_assert(ret && !qdict_size(ret));
QDECREF(resp);
/* Test repeated handshake */
resp = qmp("{ 'execute': 'qmp_capabilities' }");
resp = qtest_qmp(qts, "{ 'execute': 'qmp_capabilities' }");
g_assert_cmpstr(get_error_class(resp), ==, "CommandNotFound");
QDECREF(resp);
/* Test valid command */
resp = qmp("{ 'execute': 'query-version' }");
resp = qtest_qmp(qts, "{ 'execute': 'query-version' }");
test_version(qdict_get(resp, "return"));
QDECREF(resp);
/* Test malformed commands */
test_malformed();
test_malformed(qts);
/* Test 'id' */
resp = qmp("{ 'execute': 'query-name', 'id': 'cookie#1' }");
resp = qtest_qmp(qts, "{ 'execute': 'query-name', 'id': 'cookie#1' }");
ret = qdict_get_qdict(resp, "return");
g_assert(ret);
g_assert_cmpstr(qdict_get_try_str(resp, "id"), ==, "cookie#1");
QDECREF(resp);
/* Test command failure with 'id' */
resp = qmp("{ 'execute': 'human-monitor-command', 'id': 2 }");
resp = qtest_qmp(qts, "{ 'execute': 'human-monitor-command', 'id': 2 }");
g_assert_cmpstr(get_error_class(resp), ==, "GenericError");
g_assert_cmpint(qdict_get_int(resp, "id"), ==, 2);
QDECREF(resp);
qtest_end();
qtest_quit(qts);
}
static int query_error_class(const char *cmd)

3
tests/rtas-test.c
View File

@ -14,9 +14,10 @@ static void test_rtas_get_time_of_day(void)
time_t t1, t2;
qs = qtest_spapr_boot("-machine pseries");
global_qtest = qs->qts;
t1 = time(NULL);
ret = qrtas_get_time_of_day(qs->alloc, &tm, &ns);
ret = qrtas_get_time_of_day(qs->qts, qs->alloc, &tm, &ns);
g_assert_cmpint(ret, ==, 0);
t2 = mktimegm(&tm);
g_assert(t2 - t1 < 5); /* 5 sec max to run the test */

5
tests/rtl8139-test.c
View File

@ -35,7 +35,7 @@ static QPCIDevice *get_device(void)
{
QPCIDevice *dev;
pcibus = qpci_init_pc(NULL);
pcibus = qpci_init_pc(global_qtest, NULL);
qpci_device_foreach(pcibus, 0x10ec, 0x8139, save_fn, &dev);
g_assert(dev != NULL);
@ -197,11 +197,12 @@ int main(int argc, char **argv)
{
int ret;
qtest_start("-device rtl8139");
g_test_init(&argc, &argv, NULL);
qtest_add_func("/rtl8139/nop", nop);
qtest_add_func("/rtl8139/timer", test_init);
qtest_start("-device rtl8139");
ret = g_test_run();
qtest_end();

2
tests/sdhci-test.c
View File

@ -187,7 +187,7 @@ static QSDHCI *machine_start(const struct sdhci_t *test)
global_qtest = qtest_startf("-machine %s -device sdhci-pci",
test->machine);
s->pci.bus = qpci_init_pc(NULL);
s->pci.bus = qpci_init_pc(global_qtest, NULL);
/* Find PCI device and verify it's the right one */
s->pci.dev = qpci_device_find(s->pci.bus, QPCI_DEVFN(4, 0));

5
tests/tco-test.c
View File

@ -64,7 +64,7 @@ static void test_init(TestData *d)
global_qtest = qs;
qtest_irq_intercept_in(qs, "ioapic");
d->bus = qpci_init_pc(NULL);
d->bus = qpci_init_pc(qs, NULL);
d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
g_assert(d->dev != NULL);
@ -237,9 +237,8 @@ static void test_tco_max_timeout(void)
static QDict *get_watchdog_action(void)
{
QDict *ev = qmp("");
QDict *ev = qmp_eventwait_ref("WATCHDOG");
QDict *data;
g_assert(!strcmp(qdict_get_str(ev, "event"), "WATCHDOG"));
data = qdict_get_qdict(ev, "data");
QINCREF(data);

6
tests/tmp105-test.c
View File

@ -155,15 +155,13 @@ int main(int argc, char **argv)
s = qtest_start("-machine n800 "
"-device tmp105,bus=i2c-bus.0,id=" TMP105_TEST_ID
",address=0x49");
i2c = omap_i2c_create(OMAP2_I2C_1_BASE);
i2c = omap_i2c_create(s, OMAP2_I2C_1_BASE);
qtest_add_func("/tmp105/tx-rx", send_and_receive);
ret = g_test_run();
if (s) {
qtest_quit(s);
}
qtest_quit(s);
g_free(i2c);
return ret;

2
tests/usb-hcd-ehci-test.c
View File

@ -52,7 +52,7 @@ static void ehci_port_test(struct qhc *hc, int port, uint32_t expect)
static void test_init(void)
{
pcibus = qpci_init_pc(NULL);
pcibus = qpci_init_pc(global_qtest, NULL);
g_assert(pcibus != NULL);
qusb_pci_init_one(pcibus, &uhci1, QPCI_DEVFN(0x1d, 0), 4);

1
tests/usb-hcd-uhci-test.c
View File

@ -77,6 +77,7 @@ int main(int argc, char **argv)
"available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
global_qtest = qs->qts;
ret = g_test_run();
qtest_shutdown(qs);

4
tests/vhost-user-test.c
View File

@ -180,7 +180,7 @@ static void init_virtio_dev(TestServer *s, uint32_t features_mask)
uint32_t features;
int i;
s->bus = qpci_init_pc(NULL);
s->bus = qpci_init_pc(global_qtest, NULL);
g_assert_nonnull(s->bus);
s->dev = qvirtio_pci_device_find(s->bus, VIRTIO_ID_NET);
@ -191,7 +191,7 @@ static void init_virtio_dev(TestServer *s, uint32_t features_mask)
qvirtio_set_acknowledge(&s->dev->vdev);
qvirtio_set_driver(&s->dev->vdev);
s->alloc = pc_alloc_init();
s->alloc = pc_alloc_init(global_qtest);
for (i = 0; i < s->queues * 2; i++) {
s->vq[i] = qvirtqueue_setup(&s->dev->vdev, s->alloc, i);

1
tests/virtio-9p-test.c
View File

@ -44,6 +44,7 @@ static QVirtIO9P *qvirtio_9p_start(const char *driver)
g_printerr("virtio-9p tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
global_qtest = v9p->qs->qts;
return v9p;
}

1
tests/virtio-blk-test.c
View File

@ -77,6 +77,7 @@ static QOSState *pci_test_start(void)
g_printerr("virtio-blk tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
global_qtest = qs->qts;
unlink(tmp_path);
g_free(tmp_path);
return qs;

15
tests/virtio-net-test.c
View File

@ -54,18 +54,21 @@ static QVirtioPCIDevice *virtio_net_pci_init(QPCIBus *bus, int slot)
static QOSState *pci_test_start(int socket)
{
QOSState *qs;
const char *arch = qtest_get_arch();
const char *cmd = "-netdev socket,fd=%d,id=hs0 -device "
"virtio-net-pci,netdev=hs0";
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
return qtest_pc_boot(cmd, socket);
qs = qtest_pc_boot(cmd, socket);
} else if (strcmp(arch, "ppc64") == 0) {
qs = qtest_spapr_boot(cmd, socket);
} else {
g_printerr("virtio-net tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
if (strcmp(arch, "ppc64") == 0) {
return qtest_spapr_boot(cmd, socket);
}
g_printerr("virtio-net tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
global_qtest = qs->qts;
return qs;
}
static void driver_init(QVirtioDevice *dev)

16
tests/virtio-scsi-test.c
View File

@ -34,20 +34,22 @@ typedef struct {
static QOSState *qvirtio_scsi_start(const char *extra_opts)
{
QOSState *qs;
const char *arch = qtest_get_arch();
const char *cmd = "-drive id=drv0,if=none,file=null-co://,format=raw "
"-device virtio-scsi-pci,id=vs0 "
"-device scsi-hd,bus=vs0.0,drive=drv0 %s";
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
return qtest_pc_boot(cmd, extra_opts ? : "");
qs = qtest_pc_boot(cmd, extra_opts ? : "");
} else if (strcmp(arch, "ppc64") == 0) {
qs = qtest_spapr_boot(cmd, extra_opts ? : "");
} else {
g_printerr("virtio-scsi tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
if (strcmp(arch, "ppc64") == 0) {
return qtest_spapr_boot(cmd, extra_opts ? : "");
}
g_printerr("virtio-scsi tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
global_qtest = qs->qts;
return qs;
}
static void qvirtio_scsi_stop(QOSState *qs)

2
tests/vmgenid-test.c
View File

@ -45,7 +45,7 @@ static uint32_t acpi_find_vgia(void)
int i;
/* Wait for guest firmware to finish and start the payload. */
boot_sector_test();
boot_sector_test(global_qtest);
/* Tables should be initialized now. */
rsdp_offset = acpi_find_rsdp_address();

90
tests/wdt_ib700-test.c
View File

@ -12,108 +12,98 @@
#include "qapi/qmp/qdict.h"
#include "qemu/timer.h"
static void qmp_check_no_event(void)
static void qmp_check_no_event(QTestState *s)
{
QDict *resp = qmp("{'execute':'query-status'}");
QDict *resp = qtest_qmp(s, "{'execute':'query-status'}");
g_assert(qdict_haskey(resp, "return"));
QDECREF(resp);
}
static QDict *qmp_get_event(const char *name)
{
QDict *event = qmp("");
QDict *data;
g_assert(qdict_haskey(event, "event"));
g_assert(!strcmp(qdict_get_str(event, "event"), name));
if (qdict_haskey(event, "data")) {
data = qdict_get_qdict(event, "data");
QINCREF(data);
} else {
data = NULL;
}
QDECREF(event);
return data;
}
static QDict *ib700_program_and_wait(QTestState *s)
{
clock_step(NANOSECONDS_PER_SECOND * 40);
qmp_check_no_event();
QDict *event, *data;
qtest_clock_step(s, NANOSECONDS_PER_SECOND * 40);
qmp_check_no_event(s);
/* 2 second limit */
outb(0x443, 14);
qtest_outb(s, 0x443, 14);
/* Ping */
clock_step(NANOSECONDS_PER_SECOND);
qmp_check_no_event();
outb(0x443, 14);
qtest_clock_step(s, NANOSECONDS_PER_SECOND);
qmp_check_no_event(s);
qtest_outb(s, 0x443, 14);
/* Disable */
clock_step(NANOSECONDS_PER_SECOND);
qmp_check_no_event();
outb(0x441, 1);
clock_step(3 * NANOSECONDS_PER_SECOND);
qmp_check_no_event();
qtest_clock_step(s, NANOSECONDS_PER_SECOND);
qmp_check_no_event(s);
qtest_outb(s, 0x441, 1);
qtest_clock_step(s, 3 * NANOSECONDS_PER_SECOND);
qmp_check_no_event(s);
/* Enable and let it fire */
outb(0x443, 13);
clock_step(3 * NANOSECONDS_PER_SECOND);
qmp_check_no_event();
clock_step(2 * NANOSECONDS_PER_SECOND);
return qmp_get_event("WATCHDOG");
qtest_outb(s, 0x443, 13);
qtest_clock_step(s, 3 * NANOSECONDS_PER_SECOND);
qmp_check_no_event(s);
qtest_clock_step(s, 2 * NANOSECONDS_PER_SECOND);
event = qtest_qmp_eventwait_ref(s, "WATCHDOG");
data = qdict_get_qdict(event, "data");
QINCREF(data);
QDECREF(event);
return data;
}
static void ib700_pause(void)
{
QDict *d;
QTestState *s = qtest_start("-watchdog-action pause -device ib700");
QTestState *s = qtest_init("-watchdog-action pause -device ib700");
qtest_irq_intercept_in(s, "ioapic");
d = ib700_program_and_wait(s);
g_assert(!strcmp(qdict_get_str(d, "action"), "pause"));
QDECREF(d);
d = qmp_get_event("STOP");
QDECREF(d);
qtest_end();
qtest_qmp_eventwait(s, "STOP");
qtest_quit(s);
}
static void ib700_reset(void)
{
QDict *d;
QTestState *s = qtest_start("-watchdog-action reset -device ib700");
QTestState *s = qtest_init("-watchdog-action reset -device ib700");
qtest_irq_intercept_in(s, "ioapic");
d = ib700_program_and_wait(s);
g_assert(!strcmp(qdict_get_str(d, "action"), "reset"));
QDECREF(d);
d = qmp_get_event("RESET");
QDECREF(d);
qtest_end();
qtest_qmp_eventwait(s, "RESET");
qtest_quit(s);
}
static void ib700_shutdown(void)
{
QDict *d;
QTestState *s = qtest_start("-watchdog-action reset -no-reboot -device ib700");
QTestState *s;
s = qtest_init("-watchdog-action reset -no-reboot -device ib700");
qtest_irq_intercept_in(s, "ioapic");
d = ib700_program_and_wait(s);
g_assert(!strcmp(qdict_get_str(d, "action"), "reset"));
QDECREF(d);
d = qmp_get_event("SHUTDOWN");
QDECREF(d);
qtest_end();
qtest_qmp_eventwait(s, "SHUTDOWN");
qtest_quit(s);
}
static void ib700_none(void)
{
QDict *d;
QTestState *s = qtest_start("-watchdog-action none -device ib700");
QTestState *s = qtest_init("-watchdog-action none -device ib700");
qtest_irq_intercept_in(s, "ioapic");
d = ib700_program_and_wait(s);
g_assert(!strcmp(qdict_get_str(d, "action"), "none"));
QDECREF(d);
qtest_end();
qtest_quit(s);
}
int main(int argc, char **argv)