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More s390x patches. The first ones are fixes: A regression, missed

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compat and a missed part of the SIMD support. The others contain
 optimizations and cleanup.
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20151021-v2' into staging

More s390x patches. The first ones are fixes: A regression, missed
compat and a missed part of the SIMD support. The others contain
optimizations and cleanup.

# gpg: Signature made Wed 21 Oct 2015 11:24:48 BST using RSA key ID C6F02FAF
# gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>"
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>"

* remotes/cohuck/tags/s390x-20151021-v2:
  s390x/cmma: clean up cmma reset
  s390x: reset crypto only on clear reset and QEMU reset
  s390x: machine reset function with new ipl cpu handling
  s390x/ipl: we always have an ipl device
  s390x: unify device reset during subsystem_reset()
  s390x: flagify mcic values
  s390x/kvm: Fix vector validity bit in device machine checks
  s390x/virtio-ccw: fix 2.4 virtio compat
  util/qemu-config: fix missing machine command line options

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-10-21 15:07:42 +01:00
commit 8bfaa25fce
9 changed files with 168 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
hw/s390x/ipl.c
View File

@ -95,6 +95,11 @@ static const VMStateDescription vmstate_ipl = {
}
};
static S390IPLState *get_ipl_device(void)
{
return S390_IPL(object_resolve_path_type("", TYPE_S390_IPL, NULL));
}
static uint64_t bios_translate_addr(void *opaque, uint64_t srcaddr)
{
uint64_t dstaddr = *(uint64_t *) opaque;
@ -218,7 +223,7 @@ static Property s390_ipl_properties[] = {
* - -1 if no valid boot device was found
* - ccw id of the boot device otherwise
*/
static uint64_t s390_update_iplstate(CPUS390XState *env, S390IPLState *ipl)
static uint64_t s390_update_iplstate(S390IPLState *ipl)
{
DeviceState *dev_st;
@ -251,25 +256,19 @@ out:
return (uint32_t) (ipl->cssid << 24 | ipl->ssid << 16 | ipl->devno);
}
int s390_ipl_update_diag308(IplParameterBlock *iplb)
void s390_ipl_update_diag308(IplParameterBlock *iplb)
{
S390IPLState *ipl;
S390IPLState *ipl = get_ipl_device();
ipl = S390_IPL(object_resolve_path(TYPE_S390_IPL, NULL));
if (ipl) {
ipl->iplb = *iplb;
ipl->iplb_valid = true;
return 0;
}
return -1;
ipl->iplb = *iplb;
ipl->iplb_valid = true;
}
IplParameterBlock *s390_ipl_get_iplb(void)
{
S390IPLState *ipl;
S390IPLState *ipl = get_ipl_device();
ipl = S390_IPL(object_resolve_path(TYPE_S390_IPL, NULL));
if (!ipl || !ipl->iplb_valid) {
if (!ipl->iplb_valid) {
return NULL;
}
return &ipl->iplb;
@ -277,33 +276,33 @@ IplParameterBlock *s390_ipl_get_iplb(void)
void s390_reipl_request(void)
{
S390IPLState *ipl;
S390IPLState *ipl = get_ipl_device();
ipl = S390_IPL(object_resolve_path(TYPE_S390_IPL, NULL));
ipl->reipl_requested = true;
qemu_system_reset_request();
}
void s390_ipl_prepare_cpu(S390CPU *cpu)
{
S390IPLState *ipl = get_ipl_device();
cpu->env.psw.addr = ipl->start_addr;
cpu->env.psw.mask = IPL_PSW_MASK;
if (!ipl->kernel || ipl->iplb_valid) {
cpu->env.psw.addr = ipl->bios_start_addr;
cpu->env.regs[7] = s390_update_iplstate(ipl);
}
}
static void s390_ipl_reset(DeviceState *dev)
{
S390IPLState *ipl = S390_IPL(dev);
S390CPU *cpu = S390_CPU(qemu_get_cpu(0));
CPUS390XState *env = &cpu->env;
env->psw.addr = ipl->start_addr;
env->psw.mask = IPL_PSW_MASK;
if (!ipl->reipl_requested) {
ipl->iplb_valid = false;
}
ipl->reipl_requested = false;
if (!ipl->kernel || ipl->iplb_valid) {
env->psw.addr = ipl->bios_start_addr;
env->regs[7] = s390_update_iplstate(env, ipl);
}
s390_cpu_set_state(CPU_STATE_OPERATING, cpu);
}
static void s390_ipl_class_init(ObjectClass *klass, void *data)

5
hw/s390x/ipl.h
View File

@ -12,13 +12,16 @@
#ifndef HW_S390_IPL_H
#define HW_S390_IPL_H
#include "cpu.h"
typedef struct IplParameterBlock {
uint8_t reserved1[110];
uint16_t devno;
uint8_t reserved2[88];
} IplParameterBlock;
int s390_ipl_update_diag308(IplParameterBlock *iplb);
void s390_ipl_update_diag308(IplParameterBlock *iplb);
void s390_ipl_prepare_cpu(S390CPU *cpu);
IplParameterBlock *s390_ipl_get_iplb(void);
void s390_reipl_request(void);

44
hw/s390x/s390-virtio-ccw.c
View File

@ -35,26 +35,23 @@ typedef struct S390CcwMachineState {
bool dea_key_wrap;
} S390CcwMachineState;
static const char *const reset_dev_types[] = {
"virtual-css-bridge",
"s390-sclp-event-facility",
"s390-flic",
"diag288",
};
void subsystem_reset(void)
{
DeviceState *css, *sclp, *flic, *diag288;
DeviceState *dev;
int i;
css = DEVICE(object_resolve_path_type("", "virtual-css-bridge", NULL));
if (css) {
qdev_reset_all(css);
}
sclp = DEVICE(object_resolve_path_type("",
"s390-sclp-event-facility", NULL));
if (sclp) {
qdev_reset_all(sclp);
}
flic = DEVICE(object_resolve_path_type("", "s390-flic", NULL));
if (flic) {
qdev_reset_all(flic);
}
diag288 = DEVICE(object_resolve_path_type("", "diag288", NULL));
if (diag288) {
qdev_reset_all(diag288);
for (i = 0; i < ARRAY_SIZE(reset_dev_types); i++) {
dev = DEVICE(object_resolve_path_type("", reset_dev_types[i], NULL));
if (dev) {
qdev_reset_all(dev);
}
}
}
@ -164,6 +161,7 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data)
NMIClass *nc = NMI_CLASS(oc);
mc->init = ccw_init;
mc->reset = s390_machine_reset;
mc->block_default_type = IF_VIRTIO;
mc->no_cdrom = 1;
mc->no_floppy = 1;
@ -262,6 +260,18 @@ static const TypeInfo ccw_machine_info = {
.driver = "virtio-rng-ccw",\
.property = "max_revision",\
.value = "0",\
},{\
.driver = "virtio-net-ccw",\
.property = "max_revision",\
.value = "0",\
},{\
.driver = "virtio-scsi-ccw",\
.property = "max_revision",\
.value = "0",\
},{\
.driver = "vhost-scsi-ccw",\
.property = "max_revision",\
.value = "0",\
},
static void ccw_machine_2_4_class_init(ObjectClass *oc, void *data)

15
hw/s390x/s390-virtio.c
View File

@ -40,6 +40,7 @@
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/s390-virtio.h"
#include "hw/s390x/storage-keys.h"
#include "hw/s390x/ipl.h"
#include "cpu.h"
//#define DEBUG_S390
@ -314,6 +315,19 @@ void s390_nmi(NMIState *n, int cpu_index, Error **errp)
}
}
void s390_machine_reset(void)
{
S390CPU *ipl_cpu = S390_CPU(qemu_get_cpu(0));
qemu_devices_reset();
s390_cmma_reset();
s390_crypto_reset();
/* all cpus are stopped - configure and start the ipl cpu only */
s390_ipl_prepare_cpu(ipl_cpu);
s390_cpu_set_state(CPU_STATE_OPERATING, ipl_cpu);
}
static void s390_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@ -322,6 +336,7 @@ static void s390_machine_class_init(ObjectClass *oc, void *data)
mc->alias = "s390";
mc->desc = "VirtIO based S390 machine";
mc->init = s390_init;
mc->reset = s390_machine_reset;
mc->block_default_type = IF_VIRTIO;
mc->max_cpus = 255;
mc->no_serial = 1;

1
hw/s390x/s390-virtio.h
View File

@ -27,5 +27,6 @@ void s390_init_ipl_dev(const char *kernel_filename,
bool enforce_bios);
void s390_create_virtio_net(BusState *bus, const char *name);
void s390_nmi(NMIState *n, int cpu_index, Error **errp);
void s390_machine_reset(void);
void s390_memory_init(ram_addr_t mem_size);
#endif

65
target-s390x/cpu.h
View File

@ -1160,12 +1160,13 @@ int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
int vq, bool assign);
int kvm_s390_cpu_restart(S390CPU *cpu);
int kvm_s390_get_memslot_count(KVMState *s);
void kvm_s390_clear_cmma_callback(void *opaque);
void kvm_s390_cmma_reset(void);
int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
void kvm_s390_reset_vcpu(S390CPU *cpu);
int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
void kvm_s390_crypto_reset(void);
#else
static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
uint16_t subchannel_nr,
@ -1189,7 +1190,7 @@ static inline int kvm_s390_cpu_restart(S390CPU *cpu)
{
return -ENOSYS;
}
static inline void kvm_s390_clear_cmma_callback(void *opaque)
static inline void kvm_s390_cmma_reset(void)
{
}
static inline int kvm_s390_get_memslot_count(KVMState *s)
@ -1215,6 +1216,9 @@ static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
{
return 0;
}
static inline void kvm_s390_crypto_reset(void)
{
}
#endif
static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
@ -1225,11 +1229,10 @@ static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
return 0;
}
static inline void cmma_reset(S390CPU *cpu)
static inline void s390_cmma_reset(void)
{
if (kvm_enabled()) {
CPUState *cs = CPU(cpu);
kvm_s390_clear_cmma_callback(cs->kvm_state);
kvm_s390_cmma_reset();
}
}
@ -1261,6 +1264,13 @@ static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
}
static inline void s390_crypto_reset(void)
{
if (kvm_enabled()) {
kvm_s390_crypto_reset();
}
}
#ifdef CONFIG_KVM
static inline bool vregs_needed(void *opaque)
{
@ -1275,4 +1285,49 @@ static inline bool vregs_needed(void *opaque)
return 0;
}
#endif
/* machine check interruption code */
/* subclasses */
#define MCIC_SC_SD 0x8000000000000000ULL
#define MCIC_SC_PD 0x4000000000000000ULL
#define MCIC_SC_SR 0x2000000000000000ULL
#define MCIC_SC_CD 0x0800000000000000ULL
#define MCIC_SC_ED 0x0400000000000000ULL
#define MCIC_SC_DG 0x0100000000000000ULL
#define MCIC_SC_W 0x0080000000000000ULL
#define MCIC_SC_CP 0x0040000000000000ULL
#define MCIC_SC_SP 0x0020000000000000ULL
#define MCIC_SC_CK 0x0010000000000000ULL
/* subclass modifiers */
#define MCIC_SCM_B 0x0002000000000000ULL
#define MCIC_SCM_DA 0x0000000020000000ULL
#define MCIC_SCM_AP 0x0000000000080000ULL
/* storage errors */
#define MCIC_SE_SE 0x0000800000000000ULL
#define MCIC_SE_SC 0x0000400000000000ULL
#define MCIC_SE_KE 0x0000200000000000ULL
#define MCIC_SE_DS 0x0000100000000000ULL
#define MCIC_SE_IE 0x0000000080000000ULL
/* validity bits */
#define MCIC_VB_WP 0x0000080000000000ULL
#define MCIC_VB_MS 0x0000040000000000ULL
#define MCIC_VB_PM 0x0000020000000000ULL
#define MCIC_VB_IA 0x0000010000000000ULL
#define MCIC_VB_FA 0x0000008000000000ULL
#define MCIC_VB_VR 0x0000004000000000ULL
#define MCIC_VB_EC 0x0000002000000000ULL
#define MCIC_VB_FP 0x0000001000000000ULL
#define MCIC_VB_GR 0x0000000800000000ULL
#define MCIC_VB_CR 0x0000000400000000ULL
#define MCIC_VB_ST 0x0000000100000000ULL
#define MCIC_VB_AR 0x0000000040000000ULL
#define MCIC_VB_PR 0x0000000000200000ULL
#define MCIC_VB_FC 0x0000000000100000ULL
#define MCIC_VB_CT 0x0000000000020000ULL
#define MCIC_VB_CC 0x0000000000010000ULL
#endif

32
target-s390x/kvm.c
View File

@ -173,16 +173,15 @@ int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit)
return kvm_vm_ioctl(s, KVM_SET_DEVICE_ATTR, &attr);
}
void kvm_s390_clear_cmma_callback(void *opaque)
void kvm_s390_cmma_reset(void)
{
int rc;
KVMState *s = opaque;
struct kvm_device_attr attr = {
.group = KVM_S390_VM_MEM_CTRL,
.attr = KVM_S390_VM_MEM_CLR_CMMA,
};
rc = kvm_vm_ioctl(s, KVM_SET_DEVICE_ATTR, &attr);
rc = kvm_vm_ioctl(kvm_state, KVM_SET_DEVICE_ATTR, &attr);
trace_kvm_clear_cmma(rc);
}
@ -200,9 +199,6 @@ static void kvm_s390_enable_cmma(KVMState *s)
}
rc = kvm_vm_ioctl(s, KVM_SET_DEVICE_ATTR, &attr);
if (!rc) {
qemu_register_reset(kvm_s390_clear_cmma_callback, s);
}
trace_kvm_enable_cmma(rc);
}
@ -249,7 +245,7 @@ static void kvm_s390_init_dea_kw(void)
}
}
static void kvm_s390_init_crypto(void)
void kvm_s390_crypto_reset(void)
{
kvm_s390_init_aes_kw();
kvm_s390_init_dea_kw();
@ -301,8 +297,6 @@ void kvm_s390_reset_vcpu(S390CPU *cpu)
if (kvm_vcpu_ioctl(cs, KVM_S390_INITIAL_RESET, NULL)) {
error_report("Initial CPU reset failed on CPU %i", cs->cpu_index);
}
kvm_s390_init_crypto();
}
static int can_sync_regs(CPUState *cs, int regs)
@ -2065,12 +2059,30 @@ void kvm_s390_io_interrupt(uint16_t subchannel_id,
kvm_s390_floating_interrupt(&irq);
}
static uint64_t build_channel_report_mcic(void)
{
uint64_t mcic;
/* subclass: indicate channel report pending */
mcic = MCIC_SC_CP |
/* subclass modifiers: none */
/* storage errors: none */
/* validity bits: no damage */
MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
if (kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS)) {
mcic |= MCIC_VB_VR;
}
return mcic;
}
void kvm_s390_crw_mchk(void)
{
struct kvm_s390_irq irq = {
.type = KVM_S390_MCHK,
.u.mchk.cr14 = 1 << 28,
.u.mchk.mcic = 0x00400f1d40330000ULL,
.u.mchk.mcic = build_channel_report_mcic(),
};
kvm_s390_floating_interrupt(&irq);
}

12
target-s390x/misc_helper.c
View File

@ -127,8 +127,9 @@ static int modified_clear_reset(S390CPU *cpu)
CPU_FOREACH(t) {
run_on_cpu(t, s390_do_cpu_full_reset, t);
}
cmma_reset(cpu);
s390_cmma_reset();
subsystem_reset();
s390_crypto_reset();
scc->load_normal(CPU(cpu));
cpu_synchronize_all_post_reset();
resume_all_vcpus();
@ -145,7 +146,7 @@ static int load_normal_reset(S390CPU *cpu)
CPU_FOREACH(t) {
run_on_cpu(t, s390_do_cpu_reset, t);
}
cmma_reset(cpu);
s390_cmma_reset();
subsystem_reset();
scc->initial_cpu_reset(CPU(cpu));
scc->load_normal(CPU(cpu));
@ -233,11 +234,8 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3)
}
iplb = g_malloc0(sizeof(struct IplParameterBlock));
cpu_physical_memory_read(addr, iplb, sizeof(struct IplParameterBlock));
if (!s390_ipl_update_diag308(iplb)) {
env->regs[r1 + 1] = DIAG_308_RC_OK;
} else {
env->regs[r1 + 1] = DIAG_308_RC_INVALID;
}
s390_ipl_update_diag308(iplb);
env->regs[r1 + 1] = DIAG_308_RC_OK;
g_free(iplb);
return;
case 6:

8
util/qemu-config.c
View File

@ -219,6 +219,14 @@ static QemuOptsList machine_opts = {
.name = "suppress-vmdesc",
.type = QEMU_OPT_BOOL,
.help = "Set on to disable self-describing migration",
},{
.name = "aes-key-wrap",
.type = QEMU_OPT_BOOL,
.help = "enable/disable AES key wrapping using the CPACF wrapping key",
},{
.name = "dea-key-wrap",
.type = QEMU_OPT_BOOL,
.help = "enable/disable DEA key wrapping using the CPACF wrapping key",
},
{ /* End of list */ }
}