SPARC: Emulation of GRLIB APB UART
This device exposes one parameter: - chardev (ptr) : Pointer to a qemu character device Emulation of GrLib devices is base on the GRLIB IP Core User's Manual: http://www.gaisler.com/products/grlib/grip.pdf Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Fabien Chouteau
Blue Swirl
parent
3f10bcbb64
commit
8b1e132074
23
hw/grlib.h
23
hw/grlib.h
@ -100,4 +100,27 @@ DeviceState *grlib_gptimer_create(target_phys_addr_t base,
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return dev;
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}
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/* APB UART */
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static inline
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DeviceState *grlib_apbuart_create(target_phys_addr_t base,
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CharDriverState *serial,
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qemu_irq irq)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "grlib,apbuart");
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qdev_prop_set_chr(dev, "chrdev", serial);
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if (qdev_init(dev)) {
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return NULL;
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}
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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#endif /* ! _GRLIB_H_ */
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187
hw/grlib_apbuart.c
Normal file
187
hw/grlib_apbuart.c
Normal file
@ -0,0 +1,187 @@
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/*
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* QEMU GRLIB APB UART Emulator
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*
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* Copyright (c) 2010-2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "qemu-char.h"
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#include "trace.h"
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#define UART_REG_SIZE 20 /* Size of memory mapped registers */
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/* UART status register fields */
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#define UART_DATA_READY (1 << 0)
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#define UART_TRANSMIT_SHIFT_EMPTY (1 << 1)
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#define UART_TRANSMIT_FIFO_EMPTY (1 << 2)
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#define UART_BREAK_RECEIVED (1 << 3)
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#define UART_OVERRUN (1 << 4)
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#define UART_PARITY_ERROR (1 << 5)
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#define UART_FRAMING_ERROR (1 << 6)
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#define UART_TRANSMIT_FIFO_HALF (1 << 7)
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#define UART_RECEIVE_FIFO_HALF (1 << 8)
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#define UART_TRANSMIT_FIFO_FULL (1 << 9)
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#define UART_RECEIVE_FIFO_FULL (1 << 10)
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/* UART control register fields */
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#define UART_RECEIVE_ENABLE (1 << 0)
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#define UART_TRANSMIT_ENABLE (1 << 1)
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#define UART_RECEIVE_INTERRUPT (1 << 2)
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#define UART_TRANSMIT_INTERRUPT (1 << 3)
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#define UART_PARITY_SELECT (1 << 4)
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#define UART_PARITY_ENABLE (1 << 5)
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#define UART_FLOW_CONTROL (1 << 6)
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#define UART_LOOPBACK (1 << 7)
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#define UART_EXTERNAL_CLOCK (1 << 8)
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#define UART_RECEIVE_FIFO_INTERRUPT (1 << 9)
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#define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
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#define UART_FIFO_DEBUG_MODE (1 << 11)
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#define UART_OUTPUT_ENABLE (1 << 12)
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#define UART_FIFO_AVAILABLE (1 << 31)
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/* Memory mapped register offsets */
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#define DATA_OFFSET 0x00
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#define STATUS_OFFSET 0x04
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#define CONTROL_OFFSET 0x08
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#define SCALER_OFFSET 0x0C /* not supported */
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#define FIFO_DEBUG_OFFSET 0x10 /* not supported */
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typedef struct UART {
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SysBusDevice busdev;
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qemu_irq irq;
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CharDriverState *chr;
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/* registers */
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uint32_t receive;
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uint32_t status;
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uint32_t control;
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} UART;
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static int grlib_apbuart_can_receive(void *opaque)
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{
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UART *uart = opaque;
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return !!(uart->status & UART_DATA_READY);
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}
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static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
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{
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UART *uart = opaque;
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uart->receive = *buf;
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uart->status |= UART_DATA_READY;
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if (uart->control & UART_RECEIVE_INTERRUPT) {
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qemu_irq_pulse(uart->irq);
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}
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}
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static void grlib_apbuart_event(void *opaque, int event)
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{
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trace_grlib_apbuart_event(event);
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}
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static void
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grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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UART *uart = opaque;
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unsigned char c = 0;
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addr &= 0xff;
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/* Unit registers */
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switch (addr) {
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case DATA_OFFSET:
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c = value & 0xFF;
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qemu_chr_write(uart->chr, &c, 1);
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return;
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case STATUS_OFFSET:
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/* Read Only */
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return;
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case CONTROL_OFFSET:
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/* Not supported */
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return;
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case SCALER_OFFSET:
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/* Not supported */
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return;
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default:
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break;
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}
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trace_grlib_apbuart_unknown_register("write", addr);
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}
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static CPUReadMemoryFunc * const grlib_apbuart_read[] = {
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NULL, NULL, NULL,
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};
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static CPUWriteMemoryFunc * const grlib_apbuart_write[] = {
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NULL, NULL, grlib_apbuart_writel,
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};
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static int grlib_apbuart_init(SysBusDevice *dev)
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{
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UART *uart = FROM_SYSBUS(typeof(*uart), dev);
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int uart_regs = 0;
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qemu_chr_add_handlers(uart->chr,
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grlib_apbuart_can_receive,
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grlib_apbuart_receive,
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grlib_apbuart_event,
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uart);
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sysbus_init_irq(dev, &uart->irq);
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uart_regs = cpu_register_io_memory(grlib_apbuart_read,
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grlib_apbuart_write,
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uart, DEVICE_NATIVE_ENDIAN);
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if (uart_regs < 0) {
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return -1;
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}
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sysbus_init_mmio(dev, UART_REG_SIZE, uart_regs);
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return 0;
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}
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static SysBusDeviceInfo grlib_gptimer_info = {
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.init = grlib_apbuart_init,
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.qdev.name = "grlib,apbuart",
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.qdev.size = sizeof(UART),
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.qdev.props = (Property[]) {
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DEFINE_PROP_CHR("chrdev", UART, chr),
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DEFINE_PROP_END_OF_LIST()
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}
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};
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static void grlib_gptimer_register(void)
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{
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sysbus_register_withprop(&grlib_gptimer_info);
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}
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device_init(grlib_gptimer_register)
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@ -240,3 +240,7 @@ disable grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uin
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disable grlib_irqmp_ack(int intno) "interrupt:%d"
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disable grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
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disable grlib_irqmp_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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# hw/grlib_apbuart.c
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disable grlib_apbuart_event(int event) "event:%d"
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disable grlib_apbuart_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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