mirrors
/
qemu
mirror of https://gitlab.com/qemu-project/qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

riscv: sifive_u: Allow up to 4 CPUs to be created 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Alistair Francis 2019-03-16 01:21:29 +00:00 committed by Palmer Dabbelt
parent d9360e9688
commit 8b1d0714bf
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
hw/riscv/sifive_u.c
View File

@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive U SDK";
mc->init = riscv_sifive_u_init;
mc->max_cpus = 1;
/* The real hardware has 5 CPUs, but one of them is a small embedded power
* management CPU.
*/
mc->max_cpus = 4;
}
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)