mirror of https://gitlab.com/qemu-project/qemu
riscv: sifive_u: Allow up to 4 CPUs to be created
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
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{
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{
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = riscv_sifive_u_init;
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mc->init = riscv_sifive_u_init;
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mc->max_cpus = 1;
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/* The real hardware has 5 CPUs, but one of them is a small embedded power
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* management CPU.
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*/
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mc->max_cpus = 4;
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}
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}
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DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
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DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
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