target/microblaze: Tidy gdbstub

Use an enumeration for the gdb register mapping.  Use one
switch statement for the entire dispatch.  Drop sreg_map
and simply enumerate those cases explicitly.  Force r0 to
have value 0 and ignore writes.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/microblaze/gdbstub.c

@@ -21,58 +21,80 @@
 #include "cpu.h"
 #include "exec/gdbstub.h"
 
-int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+/*
-{
-    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-    CPUMBState *env = &cpu->env;
-    /*
  * GDB expects SREGs in the following order:
  * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
-     * They aren't stored in this order, so make a map.
+ *
  * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
  * map them to anything and return a value of 0 instead.
  */
-    static const uint8_t sreg_map[6] = {
-        SR_PC,
-        SR_MSR,
-        SR_EAR,
-        SR_ESR,
-        SR_FSR,
-        SR_BTR
-    };
 
-    /*
+enum {
-     * GDB expects registers to be reported in this order:
+    GDB_PC    = 32 + 0,
-     * R0-R31
+    GDB_MSR   = 32 + 1,
-     * PC-BTR
+    GDB_EAR   = 32 + 2,
-     * PVR0-PVR11
+    GDB_ESR   = 32 + 3,
-     * EDR-TLBHI
+    GDB_FSR   = 32 + 4,
-     * SLR-SHR
+    GDB_BTR   = 32 + 5,
-     */
+    GDB_PVR0  = 32 + 6,
-    if (n < 32) {
+    GDB_PVR11 = 32 + 17,
-        return gdb_get_reg32(mem_buf, env->regs[n]);
+    GDB_EDR   = 32 + 18,
-    } else {
+    GDB_SLR   = 32 + 25,
-        n -= 32;
+    GDB_SHR   = 32 + 26,
-        switch (n) {
+};
-        case 0 ... 5:
+
-            return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]);
+int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
-        /* PVR12 is intentionally skipped */
+{
-        case 6 ... 17:
+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-            n -= 6;
+    CPUClass *cc = CPU_GET_CLASS(cs);
-            return gdb_get_reg32(mem_buf, env->pvr.regs[n]);
+    CPUMBState *env = &cpu->env;
-        case 18:
+    uint32_t val;
-            return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]);
+
-        /* Other SRegs aren't modeled, so report a value of 0 */
+    if (n > cc->gdb_num_core_regs) {
-        case 19 ... 24:
-            return gdb_get_reg32(mem_buf, 0);
-        case 25:
-            return gdb_get_reg32(mem_buf, env->slr);
-        case 26:
-            return gdb_get_reg32(mem_buf, env->shr);
-        default:
         return 0;
     }
+
+    switch (n) {
+    case 1 ... 31:
+        val = env->regs[n];
+        break;
+    case GDB_PC:
+        val = env->sregs[SR_PC];
+        break;
+    case GDB_MSR:
+        val = env->sregs[SR_MSR];
+        break;
+    case GDB_EAR:
+        val = env->sregs[SR_EAR];
+        break;
+    case GDB_ESR:
+        val = env->sregs[SR_ESR];
+        break;
+    case GDB_FSR:
+        val = env->sregs[SR_FSR];
+        break;
+    case GDB_BTR:
+        val = env->sregs[SR_BTR];
+        break;
+    case GDB_PVR0 ... GDB_PVR11:
+        /* PVR12 is intentionally skipped */
+        val = env->pvr.regs[n - GDB_PVR0];
+        break;
+    case GDB_EDR:
+        val = env->sregs[SR_EDR];
+        break;
+    case GDB_SLR:
+        val = env->slr;
+        break;
+    case GDB_SHR:
+        val = env->shr;
+        break;
+    default:
+        /* Other SRegs aren't modeled, so report a value of 0 */
+        val = 0;
+        break;
     }
+    return gdb_get_reg32(mem_buf, val);
 }
 
 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
@@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     CPUMBState *env = &cpu->env;
     uint32_t tmp;
 
-    /*
-     * GDB expects SREGs in the following order:
-     * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
-     * They aren't stored in this order, so make a map.
-     * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
-     * map them to anything.
-     */
-    static const uint8_t sreg_map[6] = {
-        SR_PC,
-        SR_MSR,
-        SR_EAR,
-        SR_ESR,
-        SR_FSR,
-        SR_BTR
-    };
-
     if (n > cc->gdb_num_core_regs) {
         return 0;
     }
 
     tmp = ldl_p(mem_buf);
 
-    /*
-     * GDB expects registers to be reported in this order:
-     * R0-R31
-     * PC-BTR
-     * PVR0-PVR11
-     * EDR-TLBHI
-     * SLR-SHR
-     */
-    if (n < 32) {
-        env->regs[n] = tmp;
-    } else {
-        n -= 32;
     switch (n) {
-        case 0 ... 5:
+    case 1 ... 31:
-            env->sregs[sreg_map[n]] = tmp;
+        env->regs[n] = tmp;
         break;
+    case GDB_PC:
+        env->sregs[SR_PC] = tmp;
+        break;
+    case GDB_MSR:
+        env->sregs[SR_MSR] = tmp;
+        break;
+    case GDB_EAR:
+        env->sregs[SR_EAR] = tmp;
+        break;
+    case GDB_ESR:
+        env->sregs[SR_ESR] = tmp;
+        break;
+    case GDB_FSR:
+        env->sregs[SR_FSR] = tmp;
+        break;
+    case GDB_BTR:
+        env->sregs[SR_BTR] = tmp;
+        break;
+    case GDB_PVR0 ... GDB_PVR11:
         /* PVR12 is intentionally skipped */
-        case 6 ... 17:
+        env->pvr.regs[n - GDB_PVR0] = tmp;
-            n -= 6;
-            env->pvr.regs[n] = tmp;
         break;
-        /* Only EDR is modeled in these indeces, so ignore the rest */
+    case GDB_EDR:
-        case 18:
         env->sregs[SR_EDR] = tmp;
         break;
-        case 25:
+    case GDB_SLR:
         env->slr = tmp;
         break;
-        case 26:
+    case GDB_SHR:
         env->shr = tmp;
         break;
     }
-    }
     return 4;
 }