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vga-pci: add qext region to mmio

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vga: Remove unused arrays dmask4 and dmask16
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Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20141015-1' into staging

vga-pci: add qext region to mmio
vga: Remove unused arrays dmask4 and dmask16

# gpg: Signature made Wed 15 Oct 2014 10:12:06 BST using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"

* remotes/kraxel/tags/pull-vga-20141015-1:
  hw/display/vga: Remove unused arrays dmask4 and dmask16
  vga-pci: add qext region to mmio

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2014-10-16 09:26:14 +01:00
commit 8a2c263624
4 changed files with 87 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
docs/specs/standard-vga.txt
View File

@ -70,3 +70,12 @@ Likewise applies to the pci variant only for obvious reasons.
0500 - 0515 : bochs dispi interface registers, mapped flat
without index/data ports. Use (index << 1)
as offset for (16bit) register access.
0600 - 0607 : qemu extended registers. qemu 2.2+ only.
The pci revision is 2 (or greater) when
these registers are present. The registers
are 32bit.
0600 : qemu extended register region size, in bytes.
0604 : framebuffer endianness register.
- 0xbebebebe indicates big endian.
- 0x1e1e1e1e indicates little endian.

70
hw/display/vga-pci.c
View File

@ -35,10 +35,18 @@
#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
#define PCI_VGA_BOCHS_OFFSET 0x500
#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
#define PCI_VGA_QEXT_OFFSET 0x600
#define PCI_VGA_QEXT_SIZE (2 * 4)
#define PCI_VGA_MMIO_SIZE 0x1000
#define PCI_VGA_QEXT_REG_SIZE (0 * 4)
#define PCI_VGA_QEXT_REG_BYTEORDER (1 * 4)
#define PCI_VGA_QEXT_LITTLE_ENDIAN 0x1e1e1e1e
#define PCI_VGA_QEXT_BIG_ENDIAN 0xbebebebe
enum vga_pci_flags {
PCI_VGA_FLAG_ENABLE_MMIO = 1,
PCI_VGA_FLAG_ENABLE_QEXT = 2,
};
typedef struct PCIVGAState {
@ -48,6 +56,7 @@ typedef struct PCIVGAState {
MemoryRegion mmio;
MemoryRegion ioport;
MemoryRegion bochs;
MemoryRegion qext;
} PCIVGAState;
static const VMStateDescription vmstate_vga_pci = {
@ -140,6 +149,46 @@ static const MemoryRegionOps pci_vga_bochs_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
{
PCIVGAState *d = ptr;
switch (addr) {
case PCI_VGA_QEXT_REG_SIZE:
return PCI_VGA_QEXT_SIZE;
case PCI_VGA_QEXT_REG_BYTEORDER:
return d->vga.big_endian_fb ?
PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
default:
return 0;
}
}
static void pci_vga_qext_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
PCIVGAState *d = ptr;
switch (addr) {
case PCI_VGA_QEXT_REG_BYTEORDER:
if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
d->vga.big_endian_fb = true;
}
if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
d->vga.big_endian_fb = false;
}
break;
}
}
static const MemoryRegionOps pci_vga_qext_ops = {
.read = pci_vga_qext_read,
.write = pci_vga_qext_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_std_vga_initfn(PCIDevice *dev)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
@ -167,6 +216,15 @@ static int pci_std_vga_initfn(PCIDevice *dev)
&d->ioport);
memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
&d->bochs);
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
"qemu extended regs", PCI_VGA_QEXT_SIZE);
memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
&d->qext);
pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
}
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
}
@ -199,6 +257,14 @@ static int pci_secondary_vga_initfn(PCIDevice *dev)
memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
&d->bochs);
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
"qemu extended regs", PCI_VGA_QEXT_SIZE);
memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
&d->qext);
pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
}
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
@ -215,11 +281,15 @@ static void pci_secondary_vga_reset(DeviceState *dev)
static Property vga_pci_properties[] = {
DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
DEFINE_PROP_BIT("qemu-extended-regs",
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
DEFINE_PROP_END_OF_LIST(),
};
static Property secondary_pci_properties[] = {
DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
DEFINE_PROP_BIT("qemu-extended-regs",
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
DEFINE_PROP_END_OF_LIST(),
};

26
hw/display/vga.c
View File

@ -136,32 +136,6 @@ static const uint32_t mask16[16] = {
#define PAT(x) cbswap_32(x)
#endif
static const uint32_t dmask16[16] = {
PAT(0x00000000),
PAT(0x000000ff),
PAT(0x0000ff00),
PAT(0x0000ffff),
PAT(0x00ff0000),
PAT(0x00ff00ff),
PAT(0x00ffff00),
PAT(0x00ffffff),
PAT(0xff000000),
PAT(0xff0000ff),
PAT(0xff00ff00),
PAT(0xff00ffff),
PAT(0xffff0000),
PAT(0xffff00ff),
PAT(0xffffff00),
PAT(0xffffffff),
};
static const uint32_t dmask4[4] = {
PAT(0x00000000),
PAT(0x0000ffff),
PAT(0xffff0000),
PAT(0xffffffff),
};
static uint32_t expand4[256];
static uint16_t expand2[256];
static uint8_t expand4to8[16];

8
include/hw/i386/pc.h
View File

@ -306,6 +306,14 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "intel-hda",\
.property = "old_msi_addr",\
.value = "on",\
},{\
.driver = "VGA",\
.property = "qemu-extended-regs",\
.value = "off",\
},{\
.driver = "secondary-vga",\
.property = "qemu-extended-regs",\
.value = "off",\
}
#define PC_COMPAT_2_0 \