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hw/isa/piix3: Avoid Xen-specific variant of piix3_write_config()

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Subscribe to pci_bus_fire_intx_routing_notifier() instead which allows for
having a common piix3_write_config() for the PIIX3 device models.

While at it, move the subscription into machine code to facilitate resolving
TYPE_PIIX3_XEN_DEVICE.

In a possible future followup, pci_bus_fire_intx_routing_notifier() could
be adjusted in such a way that subscribing to it doesn't require
knowledge of the device firing it.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Tested-by: Chuck Zmudzinski <brchuckz@aol.com>
Message-Id: <20230312120221.99183-5-shentey@gmail.com>
Message-Id: <20230403074124.3925-6-shentey@gmail.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
This commit is contained in:
Bernhard Beschow 2023-04-03 09:41:22 +02:00 committed by Anthony PERARD
parent 60a9eb57f3
commit 89965db43c
2 changed files with 19 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hw/i386/pc_piix.c
View File

@ -90,6 +90,21 @@ static int pc_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3; return (pci_intx + slot_addend) & 3;
} }
static void piix_intx_routing_notifier_xen(PCIDevice *dev)
{
int i;
/* Scan for updates to PCI link routes (0x60-0x63). */
for (i = 0; i < PIIX_NUM_PIRQS; i++) {
uint8_t v = dev->config_read(dev, PIIX_PIRQCA + i, 1);
if (v & 0x80) {
v = 0;
}
v &= 0xf;
xen_set_pci_link_route(i, v);
}
}
/* PC hardware initialisation */ /* PC hardware initialisation */
static void pc_init1(MachineState *machine, static void pc_init1(MachineState *machine,
const char *host_type, const char *pci_type) const char *host_type, const char *pci_type)
@ -241,6 +256,9 @@ static void pc_init1(MachineState *machine,
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type);
if (xen_enabled()) { if (xen_enabled()) {
pci_device_set_intx_routing_notifier(
pci_dev, piix_intx_routing_notifier_xen);
/* /*
* Xen supports additional interrupt routes from the PCI devices to * Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also * the IOAPIC: the four pins of each PCI device on the bus are also

22
hw/isa/piix3.c
View File

@ -122,26 +122,6 @@ static void piix3_write_config(PCIDevice *dev,
} }
} }
static void piix3_write_config_xen(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
int i;
/* Scan for updates to PCI link routes (0x60-0x63). */
for (i = 0; i < len; i++) {
uint8_t v = (val >> (8 * i)) & 0xff;
if (v & 0x80) {
v = 0;
}
v &= 0xf;
if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
}
}
piix3_write_config(dev, address, val, len);
}
static void piix3_reset(DeviceState *dev) static void piix3_reset(DeviceState *dev)
{ {
PIIX3State *d = PIIX3_PCI_DEVICE(dev); PIIX3State *d = PIIX3_PCI_DEVICE(dev);
@ -405,7 +385,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data)
{ {
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix3_write_config_xen; k->config_write = piix3_write_config;
k->realize = piix3_realize; k->realize = piix3_realize;
} }