target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-13-peter.maydell@linaro.org
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@ -445,6 +445,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
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&2misc vm=%vm_dp vd=%vd_dp q=1
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VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
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VREV32 1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc
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VREV16 1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc
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VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
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VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
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@ -3547,3 +3547,58 @@ DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
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DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
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DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
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DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
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static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
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{
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int pass;
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/* Handle a 2-reg-misc operation by iterating 32 bits at a time */
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vm) & 0x10)) {
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return false;
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}
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if (!fn) {
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return false;
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}
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if ((a->vd | a->vm) & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
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TCGv_i32 tmp = neon_load_reg(a->vm, pass);
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fn(tmp, tmp);
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neon_store_reg(a->vd, pass, tmp);
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}
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return true;
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}
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static bool trans_VREV32(DisasContext *s, arg_2misc *a)
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{
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static NeonGenOneOpFn * const fn[] = {
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tcg_gen_bswap32_i32,
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gen_swap_half,
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NULL,
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NULL,
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};
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return do_2misc(s, a, fn[a->size]);
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}
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static bool trans_VREV16(DisasContext *s, arg_2misc *a)
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{
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if (a->size != 0) {
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return false;
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}
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return do_2misc(s, a, gen_rev16);
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}
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@ -4936,6 +4936,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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case NEON_2RM_AESE: case NEON_2RM_AESMC:
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case NEON_2RM_SHA1H:
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case NEON_2RM_SHA1SU1:
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case NEON_2RM_VREV32:
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case NEON_2RM_VREV16:
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/* handled by decodetree */
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return 1;
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case NEON_2RM_VTRN:
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@ -4957,16 +4959,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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for (pass = 0; pass < (q ? 4 : 2); pass++) {
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tmp = neon_load_reg(rm, pass);
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switch (op) {
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case NEON_2RM_VREV32:
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switch (size) {
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case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
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case 1: gen_swap_half(tmp, tmp); break;
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default: abort();
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}
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break;
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case NEON_2RM_VREV16:
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gen_rev16(tmp, tmp);
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break;
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case NEON_2RM_VCLS:
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switch (size) {
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case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
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@ -363,6 +363,7 @@ typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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/* Function prototype for gen_ functions for calling Neon helpers */
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typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
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typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
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typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
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typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
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