hw/cxl: Implement Physical Ports status retrieval
Add this command for both the Switch CCI in switch upstream ports. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-11-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron
Michael S. Tsirkin
parent
314f5033c6
commit
892e3479d7
@ -72,6 +72,7 @@ enum {
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#define CLEAR_POISON 0x2
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PHYSICAL_SWITCH = 0x51,
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#define IDENTIFY_SWITCH_DEVICE 0x0
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#define GET_PHYSICAL_PORT_STATE 0x1
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};
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@ -320,6 +321,131 @@ static CXLRetCode cmd_identify_switch_device(const struct cxl_cmd *cmd,
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return CXL_MBOX_SUCCESS;
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}
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/* CXL r3.0 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */
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static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
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uint8_t *payload_in,
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size_t len_in,
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uint8_t *payload_out,
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size_t *len_out,
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CXLCCI *cci)
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{
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/* CXL r3.0 Table 7-18: Get Physical Port State Request Payload */
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struct cxl_fmapi_get_phys_port_state_req_pl {
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uint8_t num_ports;
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uint8_t ports[];
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} QEMU_PACKED *in;
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/*
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* CXL r3.0 Table 7-20: Get Physical Port State Port Information Block
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* Format
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*/
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struct cxl_fmapi_port_state_info_block {
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uint8_t port_id;
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uint8_t config_state;
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uint8_t connected_device_cxl_version;
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uint8_t rsv1;
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uint8_t connected_device_type;
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uint8_t port_cxl_version_bitmask;
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uint8_t max_link_width;
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uint8_t negotiated_link_width;
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uint8_t supported_link_speeds_vector;
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uint8_t max_link_speed;
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uint8_t current_link_speed;
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uint8_t ltssm_state;
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uint8_t first_lane_num;
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uint16_t link_state;
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uint8_t supported_ld_count;
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} QEMU_PACKED;
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/* CXL r3.0 Table 7-19: Get Physical Port State Response Payload */
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struct cxl_fmapi_get_phys_port_state_resp_pl {
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uint8_t num_ports;
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uint8_t rsv1[3];
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struct cxl_fmapi_port_state_info_block ports[];
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} QEMU_PACKED *out;
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PCIBus *bus = &PCI_BRIDGE(cci->d)->sec_bus;
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PCIEPort *usp = PCIE_PORT(cci->d);
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size_t pl_size;
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int i;
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in = (struct cxl_fmapi_get_phys_port_state_req_pl *)payload_in;
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out = (struct cxl_fmapi_get_phys_port_state_resp_pl *)payload_out;
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/* Check if what was requested can fit */
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if (sizeof(*out) + sizeof(*out->ports) * in->num_ports > cci->payload_max) {
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return CXL_MBOX_INVALID_INPUT;
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}
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/* For success there should be a match for each requested */
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out->num_ports = in->num_ports;
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for (i = 0; i < in->num_ports; i++) {
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struct cxl_fmapi_port_state_info_block *port;
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/* First try to match on downstream port */
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PCIDevice *port_dev;
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uint16_t lnkcap, lnkcap2, lnksta;
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port = &out->ports[i];
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port_dev = pcie_find_port_by_pn(bus, in->ports[i]);
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if (port_dev) { /* DSP */
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PCIDevice *ds_dev = pci_bridge_get_sec_bus(PCI_BRIDGE(port_dev))
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->devices[0];
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port->config_state = 3;
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if (ds_dev) {
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if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) {
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port->connected_device_type = 5; /* Assume MLD for now */
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} else {
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port->connected_device_type = 1;
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}
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} else {
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port->connected_device_type = 0;
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}
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port->supported_ld_count = 3;
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} else if (usp->port == in->ports[i]) { /* USP */
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port_dev = PCI_DEVICE(usp);
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port->config_state = 4;
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port->connected_device_type = 0;
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} else {
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return CXL_MBOX_INVALID_INPUT;
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}
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port->port_id = in->ports[i];
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/* Information on status of this port in lnksta, lnkcap */
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if (!port_dev->exp.exp_cap) {
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return CXL_MBOX_INTERNAL_ERROR;
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}
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lnksta = port_dev->config_read(port_dev,
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port_dev->exp.exp_cap + PCI_EXP_LNKSTA,
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sizeof(lnksta));
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lnkcap = port_dev->config_read(port_dev,
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port_dev->exp.exp_cap + PCI_EXP_LNKCAP,
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sizeof(lnkcap));
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lnkcap2 = port_dev->config_read(port_dev,
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port_dev->exp.exp_cap + PCI_EXP_LNKCAP2,
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sizeof(lnkcap2));
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port->max_link_width = (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
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port->negotiated_link_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 4;
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/* No definition for SLS field in linux/pci_regs.h */
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port->supported_link_speeds_vector = (lnkcap2 & 0xFE) >> 1;
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port->max_link_speed = lnkcap & PCI_EXP_LNKCAP_SLS;
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port->current_link_speed = lnksta & PCI_EXP_LNKSTA_CLS;
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/* TODO: Track down if we can get the rest of the info */
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port->ltssm_state = 0x7;
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port->first_lane_num = 0;
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port->link_state = 0;
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port->port_cxl_version_bitmask = 0x2;
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port->connected_device_cxl_version = 0x2;
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}
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pl_size = sizeof(*out) + sizeof(*out->ports) * in->num_ports;
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*len_out = pl_size;
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return CXL_MBOX_SUCCESS;
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}
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/* 8.2.9.2.1 */
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static CXLRetCode cmd_firmware_update_get_info(const struct cxl_cmd *cmd,
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uint8_t *payload_in,
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@ -881,6 +1007,8 @@ static const struct cxl_cmd cxl_cmd_set_sw[256][256] = {
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[LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
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[PHYSICAL_SWITCH][IDENTIFY_SWITCH_DEVICE] = { "IDENTIFY_SWITCH_DEVICE",
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cmd_identify_switch_device, 0, 0 },
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[PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] = { "SWITCH_PHYSICAL_PORT_STATS",
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cmd_get_physical_port_state, ~0, 0 },
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};
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int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
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