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target/mips: Add emulation of nanoMIPS 16-bit misc instructions

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Add emulation of misc nanoMIPS 16-bit instructions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim 2018-08-02 16:16:09 +02:00 committed by Aleksandar Markovic
parent c46562fb2f
commit 8869ad02bf
1 changed files with 41 additions and 0 deletions
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41
target/mips/translate.c
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@ -16763,6 +16763,40 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
op = extract32(ctx->opcode, 10, 6);
switch (op) {
case NM_P16_MV:
rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
if (rt != 0) {
/* MOVE */
rs = NANOMIPS_EXTRACT_RS5(ctx->opcode);
gen_arith(ctx, OPC_ADDU, rt, rs, 0);
} else {
/* P16.RI */
switch (extract32(ctx->opcode, 3, 2)) {
case NM_P16_SYSCALL:
if (extract32(ctx->opcode, 2, 1) == 0) {
generate_exception_end(ctx, EXCP_SYSCALL);
} else {
generate_exception_end(ctx, EXCP_RI);
}
break;
case NM_BREAK16:
generate_exception_end(ctx, EXCP_BREAK);
break;
case NM_SDBBP16:
if (is_uhi(extract32(ctx->opcode, 0, 3))) {
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception_end(ctx, EXCP_RI);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
}
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
}
break;
case NM_P16_SHIFT:
{
@ -16842,6 +16876,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_LI16:
{
int imm = extract32(ctx->opcode, 0, 7);
imm = (imm == 0x7f ? -1 : imm);
if (rt != 0) {
tcg_gen_movi_tl(cpu_gpr[rt], imm);
}
}
break;
case NM_ANDI16:
break;