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target/arm: SCR_EL3.NS may be RES1

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With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-23 11:15:43 +01:00 committed by Peter Maydell
parent aa3cc42c01
commit 87bfbfe7e5
1 changed files with 3 additions and 0 deletions
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target/arm/helper.c
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@ -1855,6 +1855,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
if (cpu_isar_feature(aa64_sel2, cpu)) {
valid_mask |= SCR_EEL2;
} else if (cpu_isar_feature(aa64_rme, cpu)) {
/* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
value |= SCR_NS;
}
if (cpu_isar_feature(aa64_mte, cpu)) {
valid_mask |= SCR_ATA;