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Queued tcg and tcg code gen related cleanups

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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170719' into staging

Queued tcg and tcg code gen related cleanups

# gpg: Signature made Thu 20 Jul 2017 00:32:00 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-tcg-20170719:
  tcg: Pass generic CPUState to gen_intermediate_code()
  tcg/tci: enable bswap16_i64
  target/alpha: optimize gen_cvtlq() using deposit op
  target/sparc: optimize gen_op_mulscc() using deposit op
  target/sparc: optimize various functions using extract op
  target/ppc: optimize various functions using extract op
  target/m68k: optimize bcd_flags() using extract op
  target/arm: optimize aarch32 rev16
  target/arm: Optimize aarch64 rev16
  coccinelle: add a script to optimize tcg op using tcg_gen_extract()
  coccinelle: ignore ASTs pre-parsed cached C files
  tcg: Expand glue macros before stringifying helper names
  util/cacheinfo: Add missing include for ppc linux
  tcg/mips: reserve a register for the guest_base.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-07-20 11:00:10 +01:00
commit 87a60ee84f
31 changed files with 218 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
View File

@ -116,6 +116,8 @@ tags
TAGS
docker-src.*
*~
*.ast_raw
*.depend_raw
trace.h
trace.c
trace-ust.h

2
accel/tcg/translate-all.c
View File

@ -1280,7 +1280,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(&tcg_ctx);
tcg_ctx.cpu = ENV_GET_CPU(env);
gen_intermediate_code(env, tb);
gen_intermediate_code(cpu, tb);
tcg_ctx.cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc_ptr);

2
include/exec/exec-all.h
View File

@ -66,7 +66,7 @@ typedef ram_addr_t tb_page_addr_t;
#include "qemu/log.h"
void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
target_ulong *data);

17
include/exec/helper-tcg.h
View File

@ -6,31 +6,35 @@
#include "exec/helper-head.h"
/* Need one more level of indirection before stringification
to get all the macros expanded first. */
#define str(s) #s
#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \
{ .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) },
#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
{ .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) },
#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
{ .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) },
#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
{ .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) },
#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
{ .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) },
#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
{ .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) },
@ -39,6 +43,7 @@
#include "trace/generated-helpers.h"
#include "tcg-runtime.h"
#undef str
#undef DEF_HELPER_FLAGS_0
#undef DEF_HELPER_FLAGS_1
#undef DEF_HELPER_FLAGS_2

107
scripts/coccinelle/tcg_gen_extract.cocci Normal file
View File

@ -0,0 +1,107 @@
// optimize TCG using extract op
//
// Copyright: (C) 2017 Philippe Mathieu-Daudé. GPLv2+.
// Confidence: High
// Options: --macro-file scripts/cocci-macro-file.h
//
// Nikunj A Dadhania optimization:
// http://lists.nongnu.org/archive/html/qemu-devel/2017-02/msg05211.html
// Aurelien Jarno optimization:
// http://lists.nongnu.org/archive/html/qemu-devel/2017-05/msg01466.html
//
// This script can be run either using spatch locally or via a docker image:
//
// $ spatch \
// --macro-file scripts/cocci-macro-file.h \
// --sp-file scripts/coccinelle/tcg_gen_extract.cocci \
// --keep-comments --in-place \
// --use-gitgrep --dir target
//
// $ docker run --rm -v `pwd`:`pwd` -w `pwd` philmd/coccinelle \
// --macro-file scripts/cocci-macro-file.h \
// --sp-file scripts/coccinelle/tcg_gen_extract.cocci \
// --keep-comments --in-place \
// --use-gitgrep --dir target
@initialize:python@
@@
import sys
fd = sys.stderr
def debug(msg="", trailer="\n"):
fd.write("[DBG] " + msg + trailer)
def low_bits_count(value):
bits_count = 0
while (value & (1 << bits_count)):
bits_count += 1
return bits_count
def Mn(order): # Mersenne number
return (1 << order) - 1
@match@
identifier ret;
metavariable arg;
constant ofs, msk;
position shr_p, and_p;
@@
(
tcg_gen_shri_i32@shr_p
|
tcg_gen_shri_i64@shr_p
|
tcg_gen_shri_tl@shr_p
)(ret, arg, ofs);
... WHEN != ret
(
tcg_gen_andi_i32@and_p
|
tcg_gen_andi_i64@and_p
|
tcg_gen_andi_tl@and_p
)(ret, ret, msk);
@script:python verify_len depends on match@
ret_s << match.ret;
msk_s << match.msk;
shr_p << match.shr_p;
extract_len;
@@
is_optimizable = False
debug("candidate at %s:%s" % (shr_p[0].file, shr_p[0].line))
try: # only eval integer, no #define like 'SR_M' (cpp did this, else some headers are missing).
msk_v = long(msk_s.strip("UL"), 0)
msk_b = low_bits_count(msk_v)
if msk_b == 0:
debug(" value: 0x%x low_bits: %d" % (msk_v, msk_b))
else:
debug(" value: 0x%x low_bits: %d [Mersenne number: 0x%x]" % (msk_v, msk_b, Mn(msk_b)))
is_optimizable = Mn(msk_b) == msk_v # check low_bits
coccinelle.extract_len = "%d" % msk_b
debug(" candidate %s optimizable" % ("IS" if is_optimizable else "is NOT"))
except:
debug(" ERROR (check included headers?)")
cocci.include_match(is_optimizable)
debug()
@replacement depends on verify_len@
identifier match.ret;
metavariable match.arg;
constant match.ofs, match.msk;
position match.shr_p, match.and_p;
identifier verify_len.extract_len;
@@
(
-tcg_gen_shri_i32@shr_p(ret, arg, ofs);
+tcg_gen_extract_i32(ret, arg, ofs, extract_len);
... WHEN != ret
-tcg_gen_andi_i32@and_p(ret, ret, msk);
|
-tcg_gen_shri_i64@shr_p(ret, arg, ofs);
+tcg_gen_extract_i64(ret, arg, ofs, extract_len);
... WHEN != ret
-tcg_gen_andi_i64@and_p(ret, ret, msk);
|
-tcg_gen_shri_tl@shr_p(ret, arg, ofs);
+tcg_gen_extract_tl(ret, arg, ofs, extract_len);
... WHEN != ret
-tcg_gen_andi_tl@and_p(ret, ret, msk);
)

13
target/alpha/translate.c
View File

@ -783,11 +783,9 @@ static void gen_cvtlq(TCGv vc, TCGv vb)
/* The arithmetic right shift here, plus the sign-extended mask below
yields a sign-extended result without an explicit ext32s_i64. */
tcg_gen_sari_i64(tmp, vb, 32);
tcg_gen_shri_i64(vc, vb, 29);
tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
tcg_gen_andi_i64(vc, vc, 0x3fffffff);
tcg_gen_or_i64(vc, vc, tmp);
tcg_gen_shri_i64(tmp, vb, 29);
tcg_gen_sari_i64(vc, vb, 32);
tcg_gen_deposit_i64(vc, vc, tmp, 0, 30);
tcg_temp_free(tmp);
}
@ -2954,10 +2952,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
AlphaCPU *cpu = alpha_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUAlphaState *env = cs->env_ptr;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
target_ulong pc_mask;

30
target/arm/translate-a64.c
View File

@ -4043,25 +4043,13 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
TCGv_i64 tcg_rd = cpu_reg(s, rd);
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
if (sf) {
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
}
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
tcg_temp_free_i64(tcg_tmp);
}
@ -11191,10 +11179,10 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s);
}
void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
{
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;

12
target/arm/translate.c
View File

@ -343,11 +343,13 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
static void gen_rev16(TCGv_i32 var)
{
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
tcg_gen_shri_i32(tmp, var, 8);
tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
tcg_gen_and_i32(tmp, tmp, mask);
tcg_gen_and_i32(var, var, mask);
tcg_gen_shli_i32(var, var, 8);
tcg_gen_andi_i32(var, var, 0xff00ff00);
tcg_gen_or_i32(var, var, tmp);
tcg_temp_free_i32(mask);
tcg_temp_free_i32(tmp);
}
@ -11793,10 +11795,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;
@ -11810,7 +11812,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
gen_intermediate_code_a64(cpu, tb);
gen_intermediate_code_a64(cs, tb);
return;
}

4
target/arm/translate.h
View File

@ -149,7 +149,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
#ifdef TARGET_AARCH64
void a64_translate_init(void);
void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);
void gen_a64_set_pc_im(uint64_t val);
void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags);
@ -158,7 +158,7 @@ static inline void a64_translate_init(void)
{
}
static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)
{
}

7
target/cris/translate.c
View File

@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
*/
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CRISCPU *cpu = cris_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUCRISState *env = cs->env_ptr;
uint32_t pc_start;
unsigned int insn_len;
struct DisasContext ctx;
@ -3105,7 +3104,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
dc->cpu = cpu;
dc->cpu = cris_env_get_cpu(env);
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;

5
target/hppa/translate.c
View File

@ -3740,10 +3740,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return gen_illegal(ctx);
}
void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
HPPACPU *cpu = hppa_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUHPPAState *env = cs->env_ptr;
DisasContext ctx;
ExitStatus ret;
int num_insns, max_insns, i;

5
target/i386/translate.c
View File

@ -8378,10 +8378,9 @@ void tcg_x86_init(void)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = x86_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUX86State *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint32_t flags;

4
target/lm32/translate.c
View File

@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPULM32State *env = cs->env_ptr;
LM32CPU *cpu = lm32_env_get_cpu(env);
CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;

8
target/m68k/translate.c
View File

@ -1749,8 +1749,7 @@ static void bcd_flags(TCGv val)
tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
tcg_gen_shri_i32(QREG_CC_C, val, 8);
tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
}
@ -5519,10 +5518,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
M68kCPU *cpu = m68k_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUM68KState *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
int pc_offset;

4
target/microblaze/translate.c
View File

@ -1625,10 +1625,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUMBState *env = cs->env_ptr;
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
CPUState *cs = CPU(cpu);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;

5
target/mips/translate.c
View File

@ -19888,10 +19888,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUMIPSState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
target_ulong next_page_start;

4
target/moxie/translate.c
View File

@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUMoxieState *env = cs->env_ptr;
MoxieCPU *cpu = moxie_env_get_cpu(env);
CPUState *cs = CPU(cpu);
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;

5
target/nios2/translate.c
View File

@ -799,10 +799,9 @@ static void gen_exception(DisasContext *dc, uint32_t excp)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
Nios2CPU *cpu = nios2_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUNios2State *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
int num_insns;
int max_insns;

4
target/openrisc/translate.c
View File

@ -1518,10 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
}
}
void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUOpenRISCState *env = cs->env_ptr;
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;

26
target/ppc/translate.c
View File

@ -873,8 +873,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
}
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@ -1404,8 +1403,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_temp_free(inv1);
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@ -4336,8 +4334,7 @@ static void gen_mfsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -4368,8 +4365,7 @@ static void gen_mtsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -4403,8 +4399,7 @@ static void gen_mfsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -4435,8 +4430,7 @@ static void gen_mtsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -5414,8 +5408,7 @@ static void gen_mfsri(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
tcg_gen_shri_tl(t0, t0, 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, t0, 28, 4);
gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
tcg_temp_free(t0);
if (ra != 0 && ra != rd)
@ -7203,10 +7196,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
}
/*****************************************************************************/
void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUPPCState *env = cs->env_ptr;
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
target_ulong pc_start;

24
target/ppc/translate/vsx-impl.inc.c
View File

@ -1248,8 +1248,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(rt, rt, 0x7FF);
tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11);
}
static void gen_xsxexpqp(DisasContext *ctx)
@ -1262,8 +1261,7 @@ static void gen_xsxexpqp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
tcg_gen_shri_i64(xth, xbh, 48);
tcg_gen_andi_i64(xth, xth, 0x7FFF);
tcg_gen_extract_i64(xth, xbh, 48, 15);
tcg_gen_movi_i64(xtl, 0);
}
@ -1323,8 +1321,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(exp, exp, 0x7FF);
tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@ -1352,8 +1349,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(32767);
tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
tcg_gen_andi_i64(exp, exp, 0x7FFF);
tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@ -1448,10 +1444,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
tcg_gen_shri_i64(xth, xbh, 52);
tcg_gen_andi_i64(xth, xth, 0x7FF);
tcg_gen_shri_i64(xtl, xbl, 52);
tcg_gen_andi_i64(xtl, xtl, 0x7FF);
tcg_gen_extract_i64(xth, xbh, 52, 11);
tcg_gen_extract_i64(xtl, xbl, 52, 11);
}
GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
@ -1474,16 +1468,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
tcg_gen_shri_i64(exp, xbh, 52);
tcg_gen_andi_i64(exp, exp, 0x7FF);
tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
tcg_gen_or_i64(xth, xth, t0);
tcg_gen_shri_i64(exp, xbl, 52);
tcg_gen_andi_i64(exp, exp, 0x7FF);
tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);

5
target/s390x/translate.c
View File

@ -5853,10 +5853,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
return ret;
}
void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
S390CPU *cpu = s390_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUS390XState *env = cs->env_ptr;
DisasContext dc;
target_ulong pc_start;
uint64_t next_page_start;

5
target/sh4/translate.c
View File

@ -2230,10 +2230,9 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
}
#endif
void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
SuperHCPU *cpu = sh_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUSH4State *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns;

25
target/sparc/translate.c
View File

@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
tcg_gen_andi_tl(reg, reg, 0x1);
tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
}
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
tcg_gen_andi_tl(reg, reg, 0x1);
tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
}
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
tcg_gen_andi_tl(reg, reg, 0x1);
tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
}
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
tcg_gen_andi_tl(reg, reg, 0x1);
tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
}
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
@ -636,12 +632,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
// b2 = T0 & 1;
// env->y = (b2 << 31) | (env->y >> 1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
tcg_gen_shri_tl(t0, cpu_y, 1);
tcg_gen_andi_tl(t0, t0, 0x7fffffff);
tcg_gen_or_tl(t0, t0, r_temp);
tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
tcg_gen_extract_tl(t0, cpu_y, 1, 31);
tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
// b1 = N ^ V;
gen_mov_reg_N(t0, cpu_psr);
@ -5747,10 +5739,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
{
SPARCCPU *cpu = sparc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUSPARCState *env = cs->env_ptr;
target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
int num_insns;

5
target/tilegx/translate.c
View File

@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
}
}
void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
TileGXCPU *cpu = tilegx_env_get_cpu(env);
CPUTLGState *env = cs->env_ptr;
DisasContext ctx;
DisasContext *dc = &ctx;
CPUState *cs = CPU(cpu);
uint64_t pc_start = tb->pc;
uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
int num_insns = 0;

5
target/tricore/translate.c
View File

@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
}
}
void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
TriCoreCPU *cpu = tricore_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUTriCoreState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;

5
target/unicore32/translate.c
View File

@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
UniCore32CPU *cpu = uc32_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUUniCore32State *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
uint32_t next_page_start;

5
target/xtensa/translate.c
View File

@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
}
}
void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUXtensaState *env = cs->env_ptr;
DisasContext dc;
int insn_count = 0;
int max_insns = tb->cflags & CF_COUNT_MASK;

17
tcg/mips/tcg-target.inc.c
View File

@ -85,6 +85,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP2 TCG_REG_T8
#define TCG_TMP3 TCG_REG_T7
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG TCG_REG_S1
#endif
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
@ -1547,8 +1551,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
@ -1652,8 +1655,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
@ -2452,6 +2454,13 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
#ifndef CONFIG_SOFTMMU
if (guest_base) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
#endif
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
/* delay slot */

1
tcg/tci.c
View File

@ -1046,7 +1046,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
break;
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
TODO();
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg64(t0, bswap16(t1));

1
util/cacheinfo.c
View File

@ -129,6 +129,7 @@ static void arch_cache_info(int *isize, int *dsize)
}
#elif defined(_ARCH_PPC) && defined(__linux__)
# include "elf.h"
static void arch_cache_info(int *isize, int *dsize)
{