hw/intc: add goldfish-pic
Implement the goldfish pic device as defined in https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210312214145.2936082-3-laurent@vivier.eu>
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@ -67,3 +67,6 @@ config SIFIVE_CLINT
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config SIFIVE_PLIC
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bool
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config GOLDFISH_PIC
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bool
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219
hw/intc/goldfish_pic.c
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219
hw/intc/goldfish_pic.c
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@ -0,0 +1,219 @@
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/*
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* SPDX-License-Identifer: GPL-2.0-or-later
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*
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* Goldfish PIC
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*
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* (c) 2020 Laurent Vivier <laurent@vivier.eu>
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "monitor/monitor.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/intc/intc.h"
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#include "hw/intc/goldfish_pic.h"
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/* registers */
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enum {
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REG_STATUS = 0x00,
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REG_IRQ_PENDING = 0x04,
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REG_IRQ_DISABLE_ALL = 0x08,
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REG_DISABLE = 0x0c,
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REG_ENABLE = 0x10,
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};
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static bool goldfish_pic_get_statistics(InterruptStatsProvider *obj,
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uint64_t **irq_counts,
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unsigned int *nb_irqs)
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{
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GoldfishPICState *s = GOLDFISH_PIC(obj);
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*irq_counts = s->stats_irq_count;
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*nb_irqs = ARRAY_SIZE(s->stats_irq_count);
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return true;
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}
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static void goldfish_pic_print_info(InterruptStatsProvider *obj, Monitor *mon)
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{
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GoldfishPICState *s = GOLDFISH_PIC(obj);
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monitor_printf(mon, "goldfish-pic.%d: pending=0x%08x enabled=0x%08x\n",
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s->idx, s->pending, s->enabled);
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}
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static void goldfish_pic_update(GoldfishPICState *s)
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{
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if (s->pending & s->enabled) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void goldfish_irq_request(void *opaque, int irq, int level)
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{
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GoldfishPICState *s = opaque;
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trace_goldfish_irq_request(s, s->idx, irq, level);
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if (level) {
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s->pending |= 1 << irq;
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s->stats_irq_count[irq]++;
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} else {
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s->pending &= ~(1 << irq);
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}
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goldfish_pic_update(s);
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}
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static uint64_t goldfish_pic_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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GoldfishPICState *s = opaque;
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uint64_t value = 0;
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switch (addr) {
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case REG_STATUS:
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/* The number of pending interrupts (0 to 32) */
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value = ctpop32(s->pending & s->enabled);
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break;
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case REG_IRQ_PENDING:
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/* The pending interrupt mask */
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value = s->pending & s->enabled;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unimplemented register read 0x%02"HWADDR_PRIx"\n",
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__func__, addr);
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break;
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}
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trace_goldfish_pic_read(s, s->idx, addr, size, value);
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return value;
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}
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static void goldfish_pic_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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GoldfishPICState *s = opaque;
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trace_goldfish_pic_write(s, s->idx, addr, size, value);
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switch (addr) {
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case REG_IRQ_DISABLE_ALL:
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s->enabled = 0;
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s->pending = 0;
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break;
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case REG_DISABLE:
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s->enabled &= ~value;
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break;
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case REG_ENABLE:
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s->enabled |= value;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unimplemented register write 0x%02"HWADDR_PRIx"\n",
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__func__, addr);
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break;
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}
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goldfish_pic_update(s);
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}
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static const MemoryRegionOps goldfish_pic_ops = {
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.read = goldfish_pic_read,
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.write = goldfish_pic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.max_access_size = 4,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static void goldfish_pic_reset(DeviceState *dev)
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{
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GoldfishPICState *s = GOLDFISH_PIC(dev);
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int i;
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trace_goldfish_pic_reset(s, s->idx);
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s->pending = 0;
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s->enabled = 0;
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for (i = 0; i < ARRAY_SIZE(s->stats_irq_count); i++) {
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s->stats_irq_count[i] = 0;
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}
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}
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static void goldfish_pic_realize(DeviceState *dev, Error **errp)
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{
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GoldfishPICState *s = GOLDFISH_PIC(dev);
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trace_goldfish_pic_realize(s, s->idx);
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memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_pic_ops, s,
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"goldfish_pic", 0x24);
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}
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static const VMStateDescription vmstate_goldfish_pic = {
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.name = "goldfish_pic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(pending, GoldfishPICState),
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VMSTATE_UINT32(enabled, GoldfishPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void goldfish_pic_instance_init(Object *obj)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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GoldfishPICState *s = GOLDFISH_PIC(obj);
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trace_goldfish_pic_instance_init(s);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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qdev_init_gpio_in(DEVICE(obj), goldfish_irq_request, GOLDFISH_PIC_IRQ_NB);
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}
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static Property goldfish_pic_properties[] = {
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DEFINE_PROP_UINT8("index", GoldfishPICState, idx, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void goldfish_pic_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(oc);
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dc->reset = goldfish_pic_reset;
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dc->realize = goldfish_pic_realize;
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dc->vmsd = &vmstate_goldfish_pic;
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ic->get_statistics = goldfish_pic_get_statistics;
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ic->print_info = goldfish_pic_print_info;
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device_class_set_props(dc, goldfish_pic_properties);
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}
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static const TypeInfo goldfish_pic_info = {
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.name = TYPE_GOLDFISH_PIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.class_init = goldfish_pic_class_init,
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.instance_init = goldfish_pic_instance_init,
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.instance_size = sizeof(GoldfishPICState),
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_INTERRUPT_STATS_PROVIDER },
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{ }
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},
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};
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static void goldfish_pic_register_types(void)
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{
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type_register_static(&goldfish_pic_info);
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}
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type_init(goldfish_pic_register_types)
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@ -57,3 +57,4 @@ specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('xics_spapr.c', 'spapr_xi
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specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c'))
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specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
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if_true: files('spapr_xive_kvm.c'))
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specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
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@ -239,3 +239,11 @@ xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x
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# pnv_xive.c
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pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=0x%"PRIx64
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# goldfish_pic.c
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goldfish_irq_request(void *dev, int idx, int irq, int level) "pic: %p goldfish-irq.%d irq: %d level: %d"
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goldfish_pic_read(void *dev, int idx, unsigned int addr, unsigned int size, uint64_t value) "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64
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goldfish_pic_write(void *dev, int idx, unsigned int addr, unsigned int size, uint64_t value) "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64
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goldfish_pic_reset(void *dev, int idx) "pic: %p goldfish-irq.%d"
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goldfish_pic_realize(void *dev, int idx) "pic: %p goldfish-irq.%d"
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goldfish_pic_instance_init(void *dev) "pic: %p goldfish-irq"
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33
include/hw/intc/goldfish_pic.h
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33
include/hw/intc/goldfish_pic.h
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@ -0,0 +1,33 @@
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/*
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* SPDX-License-Identifer: GPL-2.0-or-later
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*
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* Goldfish PIC
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*
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* (c) 2020 Laurent Vivier <laurent@vivier.eu>
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*
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*/
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#ifndef HW_INTC_GOLDFISH_PIC_H
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#define HW_INTC_GOLDFISH_PIC_H
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#define TYPE_GOLDFISH_PIC "goldfish_pic"
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OBJECT_DECLARE_SIMPLE_TYPE(GoldfishPICState, GOLDFISH_PIC)
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#define GOLDFISH_PIC_IRQ_NB 32
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struct GoldfishPICState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t pending;
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uint32_t enabled;
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/* statistics */
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uint64_t stats_irq_count[32];
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/* for tracing */
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uint8_t idx;
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};
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#endif
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