target/arm: Move CPU state dumping routines to cpu.c
Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-11-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
Peter Maydell
parent
6cdca173ef
commit
864806156a
226
target/arm/cpu.c
226
target/arm/cpu.c
@ -19,6 +19,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/qemu-print.h"
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#include "qemu-common.h"
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#include "target/arm/idau.h"
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#include "qemu/module.h"
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@ -676,6 +677,231 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
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#endif
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}
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#ifdef TARGET_AARCH64
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static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t psr = pstate_read(env);
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int i;
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int el = arm_current_el(env);
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const char *ns_status;
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qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
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for (i = 0; i < 32; i++) {
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if (i == 31) {
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qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
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} else {
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qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
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(i + 2) % 3 ? " " : "\n");
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
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ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
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} else {
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ns_status = "";
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}
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qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
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psr,
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psr & PSTATE_N ? 'N' : '-',
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psr & PSTATE_Z ? 'Z' : '-',
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psr & PSTATE_C ? 'C' : '-',
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psr & PSTATE_V ? 'V' : '-',
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ns_status,
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el,
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psr & PSTATE_SP ? 'h' : 't');
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if (cpu_isar_feature(aa64_bti, cpu)) {
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qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
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}
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if (!(flags & CPU_DUMP_FPU)) {
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qemu_fprintf(f, "\n");
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return;
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}
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if (fp_exception_el(env, el) != 0) {
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qemu_fprintf(f, " FPU disabled\n");
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return;
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}
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qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
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vfp_get_fpcr(env), vfp_get_fpsr(env));
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if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
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int j, zcr_len = sve_zcr_len_for_el(env, el);
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for (i = 0; i <= FFR_PRED_NUM; i++) {
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bool eol;
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if (i == FFR_PRED_NUM) {
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qemu_fprintf(f, "FFR=");
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/* It's last, so end the line. */
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eol = true;
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} else {
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qemu_fprintf(f, "P%02d=", i);
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switch (zcr_len) {
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case 0:
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eol = i % 8 == 7;
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break;
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case 1:
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eol = i % 6 == 5;
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break;
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case 2:
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case 3:
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eol = i % 3 == 2;
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break;
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default:
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/* More than one quadword per predicate. */
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eol = true;
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break;
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}
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}
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for (j = zcr_len / 4; j >= 0; j--) {
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int digits;
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if (j * 4 + 4 <= zcr_len + 1) {
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digits = 16;
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} else {
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digits = (zcr_len % 4 + 1) * 4;
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}
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qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
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env->vfp.pregs[i].p[j],
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j ? ":" : eol ? "\n" : " ");
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}
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}
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for (i = 0; i < 32; i++) {
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if (zcr_len == 0) {
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qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
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i, env->vfp.zregs[i].d[1],
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env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
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} else if (zcr_len == 1) {
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qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
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":%016" PRIx64 ":%016" PRIx64 "\n",
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i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
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env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
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} else {
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for (j = zcr_len; j >= 0; j--) {
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bool odd = (zcr_len - j) % 2 != 0;
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if (j == zcr_len) {
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qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
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} else if (!odd) {
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if (j > 0) {
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qemu_fprintf(f, " [%x-%x]=", j, j - 1);
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} else {
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qemu_fprintf(f, " [%x]=", j);
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}
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}
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qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
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env->vfp.zregs[i].d[j * 2 + 1],
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env->vfp.zregs[i].d[j * 2],
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odd || j == 0 ? "\n" : ":");
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}
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}
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}
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} else {
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for (i = 0; i < 32; i++) {
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uint64_t *q = aa64_vfp_qreg(env, i);
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qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
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i, q[1], q[0], (i & 1 ? "\n" : " "));
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}
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}
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}
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#else
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static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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g_assert_not_reached();
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}
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#endif
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static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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int i;
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if (is_a64(env)) {
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aarch64_cpu_dump_state(cs, f, flags);
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return;
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}
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for (i = 0; i < 16; i++) {
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qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
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if ((i % 4) == 3) {
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qemu_fprintf(f, "\n");
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} else {
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qemu_fprintf(f, " ");
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}
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}
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if (arm_feature(env, ARM_FEATURE_M)) {
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uint32_t xpsr = xpsr_read(env);
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const char *mode;
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const char *ns_status = "";
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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ns_status = env->v7m.secure ? "S " : "NS ";
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}
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if (xpsr & XPSR_EXCP) {
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mode = "handler";
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} else {
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if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
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mode = "unpriv-thread";
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} else {
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mode = "priv-thread";
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}
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}
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qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
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xpsr,
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xpsr & XPSR_N ? 'N' : '-',
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xpsr & XPSR_Z ? 'Z' : '-',
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xpsr & XPSR_C ? 'C' : '-',
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xpsr & XPSR_V ? 'V' : '-',
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xpsr & XPSR_T ? 'T' : 'A',
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ns_status,
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mode);
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} else {
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uint32_t psr = cpsr_read(env);
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const char *ns_status = "";
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if (arm_feature(env, ARM_FEATURE_EL3) &&
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(psr & CPSR_M) != ARM_CPU_MODE_MON) {
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ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
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}
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qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
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psr,
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psr & CPSR_N ? 'N' : '-',
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psr & CPSR_Z ? 'Z' : '-',
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psr & CPSR_C ? 'C' : '-',
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psr & CPSR_V ? 'V' : '-',
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psr & CPSR_T ? 'T' : 'A',
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ns_status,
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aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
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}
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if (flags & CPU_DUMP_FPU) {
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int numvfpregs = 0;
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if (arm_feature(env, ARM_FEATURE_VFP)) {
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numvfpregs += 16;
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}
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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numvfpregs += 16;
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}
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for (i = 0; i < numvfpregs; i++) {
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uint64_t v = *aa32_vfp_dreg(env, i);
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qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
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i * 2, (uint32_t)v,
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i * 2 + 1, (uint32_t)(v >> 32),
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i, v);
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}
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qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
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}
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}
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uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
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{
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uint32_t Aff1 = idx / clustersz;
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@ -929,8 +929,6 @@ void arm_cpu_do_interrupt(CPUState *cpu);
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void arm_v7m_cpu_do_interrupt(CPUState *cpu);
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bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags);
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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@ -27,7 +27,6 @@
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#include "translate.h"
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#include "internals.h"
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#include "qemu/host-utils.h"
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#include "qemu/qemu-print.h"
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#include "hw/semihosting/semihost.h"
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#include "exec/gen-icount.h"
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@ -152,133 +151,6 @@ static void set_btype(DisasContext *s, int val)
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s->btype = -1;
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}
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t psr = pstate_read(env);
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int i;
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int el = arm_current_el(env);
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const char *ns_status;
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qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
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for (i = 0; i < 32; i++) {
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if (i == 31) {
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qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
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} else {
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qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
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(i + 2) % 3 ? " " : "\n");
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
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ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
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} else {
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ns_status = "";
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}
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qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
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psr,
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psr & PSTATE_N ? 'N' : '-',
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psr & PSTATE_Z ? 'Z' : '-',
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psr & PSTATE_C ? 'C' : '-',
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psr & PSTATE_V ? 'V' : '-',
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ns_status,
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el,
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psr & PSTATE_SP ? 'h' : 't');
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if (cpu_isar_feature(aa64_bti, cpu)) {
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qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
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}
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if (!(flags & CPU_DUMP_FPU)) {
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qemu_fprintf(f, "\n");
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return;
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}
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if (fp_exception_el(env, el) != 0) {
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qemu_fprintf(f, " FPU disabled\n");
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return;
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}
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qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
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vfp_get_fpcr(env), vfp_get_fpsr(env));
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if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
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int j, zcr_len = sve_zcr_len_for_el(env, el);
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for (i = 0; i <= FFR_PRED_NUM; i++) {
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bool eol;
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if (i == FFR_PRED_NUM) {
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qemu_fprintf(f, "FFR=");
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/* It's last, so end the line. */
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eol = true;
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} else {
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qemu_fprintf(f, "P%02d=", i);
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switch (zcr_len) {
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case 0:
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eol = i % 8 == 7;
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break;
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case 1:
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eol = i % 6 == 5;
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break;
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case 2:
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case 3:
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eol = i % 3 == 2;
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break;
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default:
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/* More than one quadword per predicate. */
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eol = true;
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break;
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}
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}
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for (j = zcr_len / 4; j >= 0; j--) {
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int digits;
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if (j * 4 + 4 <= zcr_len + 1) {
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digits = 16;
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} else {
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digits = (zcr_len % 4 + 1) * 4;
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}
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qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
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env->vfp.pregs[i].p[j],
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j ? ":" : eol ? "\n" : " ");
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}
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}
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for (i = 0; i < 32; i++) {
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if (zcr_len == 0) {
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qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
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i, env->vfp.zregs[i].d[1],
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env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
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} else if (zcr_len == 1) {
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qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
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":%016" PRIx64 ":%016" PRIx64 "\n",
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i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
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env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
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} else {
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for (j = zcr_len; j >= 0; j--) {
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bool odd = (zcr_len - j) % 2 != 0;
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if (j == zcr_len) {
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qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
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} else if (!odd) {
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if (j > 0) {
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qemu_fprintf(f, " [%x-%x]=", j, j - 1);
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} else {
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qemu_fprintf(f, " [%x]=", j);
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}
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}
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qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
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env->vfp.zregs[i].d[j * 2 + 1],
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env->vfp.zregs[i].d[j * 2],
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odd || j == 0 ? "\n" : ":");
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}
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}
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}
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} else {
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for (i = 0; i < 32; i++) {
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uint64_t *q = aa64_vfp_qreg(env, i);
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qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
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i, q[1], q[0], (i & 1 ? "\n" : " "));
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}
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}
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}
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void gen_a64_set_pc_im(uint64_t val)
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{
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tcg_gen_movi_i64(cpu_pc, val);
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@ -28,7 +28,6 @@
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#include "tcg-op-gvec.h"
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#include "qemu/log.h"
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#include "qemu/bitops.h"
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#include "qemu/qemu-print.h"
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#include "arm_ldst.h"
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#include "hw/semihosting/semihost.h"
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@ -12342,93 +12341,6 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
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translator_loop(ops, &dc.base, cpu, tb, max_insns);
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}
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void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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int i;
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if (is_a64(env)) {
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aarch64_cpu_dump_state(cs, f, flags);
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return;
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}
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for (i = 0; i < 16; i++) {
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qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
|
||||
if ((i % 4) == 3) {
|
||||
qemu_fprintf(f, "\n");
|
||||
} else {
|
||||
qemu_fprintf(f, " ");
|
||||
}
|
||||
}
|
||||
|
||||
if (arm_feature(env, ARM_FEATURE_M)) {
|
||||
uint32_t xpsr = xpsr_read(env);
|
||||
const char *mode;
|
||||
const char *ns_status = "";
|
||||
|
||||
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
|
||||
ns_status = env->v7m.secure ? "S " : "NS ";
|
||||
}
|
||||
|
||||
if (xpsr & XPSR_EXCP) {
|
||||
mode = "handler";
|
||||
} else {
|
||||
if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
|
||||
mode = "unpriv-thread";
|
||||
} else {
|
||||
mode = "priv-thread";
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
|
||||
xpsr,
|
||||
xpsr & XPSR_N ? 'N' : '-',
|
||||
xpsr & XPSR_Z ? 'Z' : '-',
|
||||
xpsr & XPSR_C ? 'C' : '-',
|
||||
xpsr & XPSR_V ? 'V' : '-',
|
||||
xpsr & XPSR_T ? 'T' : 'A',
|
||||
ns_status,
|
||||
mode);
|
||||
} else {
|
||||
uint32_t psr = cpsr_read(env);
|
||||
const char *ns_status = "";
|
||||
|
||||
if (arm_feature(env, ARM_FEATURE_EL3) &&
|
||||
(psr & CPSR_M) != ARM_CPU_MODE_MON) {
|
||||
ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
|
||||
}
|
||||
|
||||
qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
|
||||
psr,
|
||||
psr & CPSR_N ? 'N' : '-',
|
||||
psr & CPSR_Z ? 'Z' : '-',
|
||||
psr & CPSR_C ? 'C' : '-',
|
||||
psr & CPSR_V ? 'V' : '-',
|
||||
psr & CPSR_T ? 'T' : 'A',
|
||||
ns_status,
|
||||
aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
|
||||
}
|
||||
|
||||
if (flags & CPU_DUMP_FPU) {
|
||||
int numvfpregs = 0;
|
||||
if (arm_feature(env, ARM_FEATURE_VFP)) {
|
||||
numvfpregs += 16;
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
||||
numvfpregs += 16;
|
||||
}
|
||||
for (i = 0; i < numvfpregs; i++) {
|
||||
uint64_t v = *aa32_vfp_dreg(env, i);
|
||||
qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
|
||||
i * 2, (uint32_t)v,
|
||||
i * 2 + 1, (uint32_t)(v >> 32),
|
||||
i, v);
|
||||
}
|
||||
qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
|
||||
}
|
||||
}
|
||||
|
||||
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
|
||||
target_ulong *data)
|
||||
{
|
||||
|
||||
@ -169,7 +169,6 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
|
||||
#ifdef TARGET_AARCH64
|
||||
void a64_translate_init(void);
|
||||
void gen_a64_set_pc_im(uint64_t val);
|
||||
void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags);
|
||||
extern const TranslatorOps aarch64_translator_ops;
|
||||
#else
|
||||
static inline void a64_translate_init(void)
|
||||
@ -179,10 +178,6 @@ static inline void a64_translate_init(void)
|
||||
static inline void gen_a64_set_pc_im(uint64_t val)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void arm_test_cc(DisasCompare *cmp, int cc);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user