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target/arm: Convert Add/subtract (immediate with tags) to decodetree

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Convert the ADDG and SUBG (immediate) instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-8-peter.maydell@linaro.org
[PMM: Rebased; use TRANS_FEAT()]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-12 15:40:53 +01:00 committed by Peter Maydell
parent 3ce7b5ea73
commit 86002eccb9
2 changed files with 19 additions and 27 deletions
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8
target/arm/tcg/a64.decode
View File

@ -48,3 +48,11 @@ SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm
SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12
SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm
SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
# Add/subtract (immediate with tags)
&rri_tag rd rn uimm6 uimm4
@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag
ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag

38
target/arm/tcg/translate-a64.c
View File

@ -4244,49 +4244,36 @@ TRANS(SUBS_i, gen_rri, a, 0, 1, a->sf ? gen_sub64_CC : gen_sub32_CC)
/*
* Add/subtract (immediate, with tags)
*
* 31 30 29 28 23 22 21 16 14 10 9 5 4 0
* +--+--+--+-------------+--+---------+--+-------+-----+-----+
* |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
* +--+--+--+-------------+--+---------+--+-------+-----+-----+
*
* op: 0 -> add, 1 -> sub
*/
static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn)
static bool gen_add_sub_imm_with_tags(DisasContext *s, arg_rri_tag *a,
bool sub_op)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int uimm4 = extract32(insn, 10, 4);
int uimm6 = extract32(insn, 16, 6);
bool sub_op = extract32(insn, 30, 1);
TCGv_i64 tcg_rn, tcg_rd;
int imm;
/* Test all of sf=1, S=0, o2=0, o3=0. */
if ((insn & 0xa040c000u) != 0x80000000u ||
!dc_isar_feature(aa64_mte_insn_reg, s)) {
unallocated_encoding(s);
return;
}
imm = uimm6 << LOG2_TAG_GRANULE;
imm = a->uimm6 << LOG2_TAG_GRANULE;
if (sub_op) {
imm = -imm;
}
tcg_rn = cpu_reg_sp(s, rn);
tcg_rd = cpu_reg_sp(s, rd);
tcg_rn = cpu_reg_sp(s, a->rn);
tcg_rd = cpu_reg_sp(s, a->rd);
if (s->ata) {
gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn,
tcg_constant_i32(imm),
tcg_constant_i32(uimm4));
tcg_constant_i32(a->uimm4));
} else {
tcg_gen_addi_i64(tcg_rd, tcg_rn, imm);
gen_address_with_allocation_tag0(tcg_rd, tcg_rd);
}
return true;
}
TRANS_FEAT(ADDG_i, aa64_mte_insn_reg, gen_add_sub_imm_with_tags, a, false)
TRANS_FEAT(SUBG_i, aa64_mte_insn_reg, gen_add_sub_imm_with_tags, a, true)
/* The input should be a value in the bottom e bits (with higher
* bits zero); returns that value replicated into every element
* of size e in a 64 bit integer.
@ -4638,9 +4625,6 @@ static void disas_extract(DisasContext *s, uint32_t insn)
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 23, 6)) {
case 0x23: /* Add/subtract (immediate, with tags) */
disas_add_sub_imm_with_tags(s, insn);
break;
case 0x24: /* Logical (immediate) */
disas_logic_imm(s, insn);
break;