mirror of https://gitlab.com/qemu-project/qemu
fdc: Introduce fdctrl->phase
The floppy controller spec describes three different controller phases, which are currently not explicitly modelled in our emulation. Instead, each phase is represented by a combination of flags in registers. This patch makes explicit in which phase the controller currently is. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Message-id: 1432214378-31891-4-git-send-email-kwolf@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
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@ -495,6 +495,33 @@ enum {
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FD_DIR_DSKCHG = 0x80,
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FD_DIR_DSKCHG = 0x80,
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};
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};
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/*
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* See chapter 5.0 "Controller phases" of the spec:
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*
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* Command phase:
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* The host writes a command and its parameters into the FIFO. The command
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* phase is completed when all parameters for the command have been supplied,
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* and execution phase is entered.
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*
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* Execution phase:
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* Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
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* contains the payload now, otherwise it's unused. When all bytes of the
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* required data have been transferred, the state is switched to either result
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* phase (if the command produces status bytes) or directly back into the
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* command phase for the next command.
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*
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* Result phase:
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* The host reads out the FIFO, which contains one or more result bytes now.
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*/
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enum {
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/* Only for migration: reconstruct phase from registers like qemu 2.3 */
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FD_PHASE_RECONSTRUCT = 0,
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FD_PHASE_COMMAND = 1,
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FD_PHASE_EXECUTION = 2,
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FD_PHASE_RESULT = 3,
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};
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#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
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#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
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#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
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#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
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@ -504,6 +531,7 @@ struct FDCtrl {
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/* Controller state */
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/* Controller state */
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QEMUTimer *result_timer;
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QEMUTimer *result_timer;
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int dma_chann;
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int dma_chann;
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uint8_t phase;
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/* Controller's identification */
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/* Controller's identification */
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uint8_t version;
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uint8_t version;
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/* HW */
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/* HW */
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@ -744,6 +772,28 @@ static const VMStateDescription vmstate_fdrive = {
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}
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}
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};
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};
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/*
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* Reconstructs the phase from register values according to the logic that was
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* implemented in qemu 2.3. This is the default value that is used if the phase
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* subsection is not present on migration.
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*
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* Don't change this function to reflect newer qemu versions, it is part of
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* the migration ABI.
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*/
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static int reconstruct_phase(FDCtrl *fdctrl)
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{
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if (fdctrl->msr & FD_MSR_NONDMA) {
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return FD_PHASE_EXECUTION;
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} else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
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/* qemu 2.3 disabled RQM only during DMA transfers */
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return FD_PHASE_EXECUTION;
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} else if (fdctrl->msr & FD_MSR_DIO) {
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return FD_PHASE_RESULT;
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} else {
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return FD_PHASE_COMMAND;
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}
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}
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static void fdc_pre_save(void *opaque)
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static void fdc_pre_save(void *opaque)
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{
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{
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FDCtrl *s = opaque;
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FDCtrl *s = opaque;
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@ -751,12 +801,24 @@ static void fdc_pre_save(void *opaque)
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s->dor_vmstate = s->dor | GET_CUR_DRV(s);
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s->dor_vmstate = s->dor | GET_CUR_DRV(s);
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}
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}
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static int fdc_pre_load(void *opaque)
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{
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FDCtrl *s = opaque;
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s->phase = FD_PHASE_RECONSTRUCT;
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return 0;
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}
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static int fdc_post_load(void *opaque, int version_id)
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static int fdc_post_load(void *opaque, int version_id)
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{
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{
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FDCtrl *s = opaque;
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FDCtrl *s = opaque;
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SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
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SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
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s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
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s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
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if (s->phase == FD_PHASE_RECONSTRUCT) {
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s->phase = reconstruct_phase(s);
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}
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return 0;
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return 0;
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}
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}
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@ -794,11 +856,29 @@ static const VMStateDescription vmstate_fdc_result_timer = {
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}
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}
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};
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};
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static bool fdc_phase_needed(void *opaque)
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{
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FDCtrl *fdctrl = opaque;
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return reconstruct_phase(fdctrl) != fdctrl->phase;
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}
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static const VMStateDescription vmstate_fdc_phase = {
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.name = "fdc/phase",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(phase, FDCtrl),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_fdc = {
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static const VMStateDescription vmstate_fdc = {
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.name = "fdc",
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.name = "fdc",
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.version_id = 2,
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id = 2,
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.pre_save = fdc_pre_save,
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.pre_save = fdc_pre_save,
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.pre_load = fdc_pre_load,
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.post_load = fdc_post_load,
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.post_load = fdc_post_load,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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/* Controller State */
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/* Controller State */
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@ -838,6 +918,9 @@ static const VMStateDescription vmstate_fdc = {
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} , {
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} , {
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.vmsd = &vmstate_fdc_result_timer,
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.vmsd = &vmstate_fdc_result_timer,
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.needed = fdc_result_timer_needed,
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.needed = fdc_result_timer_needed,
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} , {
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.vmsd = &vmstate_fdc_phase,
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.needed = fdc_phase_needed,
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} , {
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} , {
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/* empty */
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/* empty */
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}
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}
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@ -1137,6 +1220,7 @@ static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
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/* Clear the FIFO and update the state for receiving the next command */
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/* Clear the FIFO and update the state for receiving the next command */
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static void fdctrl_to_command_phase(FDCtrl *fdctrl)
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static void fdctrl_to_command_phase(FDCtrl *fdctrl)
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{
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{
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fdctrl->phase = FD_PHASE_COMMAND;
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fdctrl->data_dir = FD_DIR_WRITE;
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fdctrl->data_dir = FD_DIR_WRITE;
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fdctrl->data_pos = 0;
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fdctrl->data_pos = 0;
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fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
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fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
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@ -1146,6 +1230,7 @@ static void fdctrl_to_command_phase(FDCtrl *fdctrl)
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* @fifo_len is the number of result bytes to be read out. */
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* @fifo_len is the number of result bytes to be read out. */
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static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
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static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
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{
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{
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fdctrl->phase = FD_PHASE_RESULT;
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fdctrl->data_dir = FD_DIR_READ;
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fdctrl->data_dir = FD_DIR_READ;
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fdctrl->data_len = fifo_len;
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fdctrl->data_len = fifo_len;
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fdctrl->data_pos = 0;
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fdctrl->data_pos = 0;
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@ -1912,6 +1997,9 @@ static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
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fdctrl_raise_irq(fdctrl);
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fdctrl_raise_irq(fdctrl);
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}
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}
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/*
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* Handlers for the execution phase of each command
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*/
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static const struct {
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static const struct {
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uint8_t value;
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uint8_t value;
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uint8_t mask;
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uint8_t mask;
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@ -2015,6 +2103,7 @@ static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
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/* We now have all parameters
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/* We now have all parameters
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* and will be able to treat the command
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* and will be able to treat the command
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*/
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*/
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fdctrl->phase = FD_PHASE_EXECUTION;
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if (fdctrl->data_state & FD_STATE_FORMAT) {
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if (fdctrl->data_state & FD_STATE_FORMAT) {
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fdctrl_format_sector(fdctrl);
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fdctrl_format_sector(fdctrl);
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return;
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return;
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