RISC-V: Support 64 bit start address
Even though the start address in ROM code is declared as a 64 bit address for RV64, it can't be used as upper bits are set to zero in ROM code. Update the ROM code correctly to reflect the 64bit value. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-5-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
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uint32_t fdt_load_addr, void *fdt)
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{
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int i;
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uint32_t start_addr_hi32 = 0x00000000;
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#if defined(TARGET_RISCV64)
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start_addr_hi32 = start_addr >> 32;
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#endif
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/* reset vector */
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uint32_t reset_vec[10] = {
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0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
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@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
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#endif
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0x00028067, /* jr t0 */
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start_addr, /* start: .dword */
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0x00000000,
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start_addr_hi32,
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fdt_load_addr, /* fdt_laddr: .dword */
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0x00000000,
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/* fw_dyn: */
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@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine)
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *flash0 = g_new(MemoryRegion, 1);
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target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
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uint32_t start_addr_hi32 = 0x00000000;
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int i;
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uint32_t fdt_load_addr;
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uint64_t kernel_entry;
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@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine)
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/* Compute the fdt load address in dram */
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fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
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machine->ram_size, s->fdt);
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#if defined(TARGET_RISCV64)
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start_addr_hi32 = start_addr >> 32;
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#endif
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/* reset vector */
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uint32_t reset_vec[11] = {
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@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine)
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#endif
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0x00028067, /* jr t0 */
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start_addr, /* start: .dword */
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0x00000000,
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start_addr_hi32,
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fdt_load_addr, /* fdt_laddr: .dword */
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0x00000000,
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/* fw_dyn: */
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