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net: cadence_gem: Add macro with max number of descriptor words

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Add macro with max number of DMA descriptor words.
No functional change.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2018-10-11 04:19:23 +02:00 committed by Peter Maydell
parent f02361822f
commit 8568313f3b
2 changed files with 6 additions and 3 deletions
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4
hw/net/cadence_gem.c
View File

@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
*/ */
static void gem_transmit(CadenceGEMState *s) static void gem_transmit(CadenceGEMState *s)
{ {
uint32_t desc[2]; uint32_t desc[DESC_MAX_NUM_WORDS];
hwaddr packet_desc_addr; hwaddr packet_desc_addr;
uint8_t tx_packet[2048]; uint8_t tx_packet[2048];
uint8_t *p; uint8_t *p;
@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s)
/* Last descriptor for this packet; hand the whole thing off */ /* Last descriptor for this packet; hand the whole thing off */
if (tx_desc_get_last(desc)) { if (tx_desc_get_last(desc)) {
uint32_t desc_first[2]; uint32_t desc_first[DESC_MAX_NUM_WORDS];
/* Modify the 1st descriptor of this packet to be owned by /* Modify the 1st descriptor of this packet to be owned by
* the processor. * the processor.

5
include/hw/net/cadence_gem.h
View File

@ -32,6 +32,9 @@
#define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
/* Max number of words in a DMA descriptor. */
#define DESC_MAX_NUM_WORDS 2
#define MAX_PRIORITY_QUEUES 8 #define MAX_PRIORITY_QUEUES 8
#define MAX_TYPE1_SCREENERS 16 #define MAX_TYPE1_SCREENERS 16
#define MAX_TYPE2_SCREENERS 16 #define MAX_TYPE2_SCREENERS 16
@ -74,7 +77,7 @@ typedef struct CadenceGEMState {
uint8_t can_rx_state; /* Debug only */ uint8_t can_rx_state; /* Debug only */
uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
bool sar_active[4]; bool sar_active[4];
} CadenceGEMState; } CadenceGEMState;