target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -2286,6 +2286,12 @@ done_syscall:
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queue_signal(env, info.si_signo, &info);
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queue_signal(env, info.si_signo, &info);
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}
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}
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break;
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break;
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case EXCP_DSPDIS:
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLOPC;
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queue_signal(env, info.si_signo, &info);
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break;
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default:
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default:
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// error:
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// error:
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fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
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fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
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@ -415,7 +415,7 @@ struct CPUMIPSState {
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int error_code;
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int error_code;
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uint32_t hflags; /* CPU State */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x007FF
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#define MIPS_HFLAG_TMASK 0xC07FF
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#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
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#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
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/* The KSU flags must be the lowest bits in hflags. The flag order
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/* The KSU flags must be the lowest bits in hflags. The flag order
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must be the same as defined for CP0 Status. This allows to use
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must be the same as defined for CP0 Status. This allows to use
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@ -453,6 +453,9 @@ struct CPUMIPSState {
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#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
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#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
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#define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
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#define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
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#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
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#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
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/* MIPS DSP resources access. */
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#define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */
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#define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */
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target_ulong btarget; /* Jump / branch target */
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target_ulong btarget; /* Jump / branch target */
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target_ulong bcond; /* Branch condition (if needed) */
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target_ulong bcond; /* Branch condition (if needed) */
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@ -610,8 +613,9 @@ enum {
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EXCP_MDMX,
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EXCP_MDMX,
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EXCP_C2E,
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EXCP_C2E,
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EXCP_CACHE, /* 32 */
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EXCP_CACHE, /* 32 */
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EXCP_DSPDIS,
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EXCP_LAST = EXCP_CACHE,
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EXCP_LAST = EXCP_DSPDIS,
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};
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};
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/* Dummy exception for conditional stores. */
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/* Dummy exception for conditional stores. */
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#define EXCP_SC 0x100
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#define EXCP_SC 0x100
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@ -772,6 +776,21 @@ static inline void compute_hflags(CPUMIPSState *env)
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if (env->CP0_Status & (1 << CP0St_FR)) {
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if (env->CP0_Status & (1 << CP0St_FR)) {
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env->hflags |= MIPS_HFLAG_F64;
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env->hflags |= MIPS_HFLAG_F64;
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}
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}
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if (env->insn_flags & ASE_DSPR2) {
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/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
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so enable to access DSPR2 resources. */
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
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}
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} else if (env->insn_flags & ASE_DSP) {
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/* Enables access MIPS DSP resources, now our cpu is DSP ASE,
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so enable to access DSP resources. */
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP;
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}
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}
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if (env->insn_flags & ISA_MIPS32R2) {
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if (env->insn_flags & ISA_MIPS32R2) {
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if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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env->hflags |= MIPS_HFLAG_COP1X;
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env->hflags |= MIPS_HFLAG_COP1X;
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@ -592,6 +592,9 @@ void do_interrupt (CPUMIPSState *env)
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case EXCP_THREAD:
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case EXCP_THREAD:
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cause = 25;
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cause = 25;
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goto set_EPC;
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goto set_EPC;
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case EXCP_DSPDIS:
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cause = 26;
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goto set_EPC;
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case EXCP_CACHE:
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case EXCP_CACHE:
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cause = 30;
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cause = 30;
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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@ -948,6 +948,24 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs)
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generate_exception(ctx, EXCP_RI);
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generate_exception(ctx, EXCP_RI);
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}
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}
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/* Verify that the processor is running with DSP instructions enabled.
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This is enabled by CP0 Status register MX(24) bit.
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*/
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static inline void check_dsp(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
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generate_exception(ctx, EXCP_DSPDIS);
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}
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}
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static inline void check_dspr2(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
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generate_exception(ctx, EXCP_DSPDIS);
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}
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}
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/* This code generates a "reserved instruction" exception if the
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/* This code generates a "reserved instruction" exception if the
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CPU does not support the instruction set corresponding to flags. */
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CPU does not support the instruction set corresponding to flags. */
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static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags)
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static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags)
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@ -13209,6 +13227,11 @@ void cpu_state_reset(CPUMIPSState *env)
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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env->CP0_Status |= (1 << CP0St_CU1);
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env->CP0_Status |= (1 << CP0St_CU1);
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}
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}
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if (env->cpu_model->insn_flags & ASE_DSPR2) {
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env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
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} else if (env->cpu_model->insn_flags & ASE_DSP) {
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env->hflags |= MIPS_HFLAG_DSP;
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}
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#else
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#else
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if (env->hflags & MIPS_HFLAG_BMASK) {
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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/* If the exception was raised from a delay slot,
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