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target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

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The CACHEE opcode "requires CP0 privilege".

The pseudocode checks in the ISA manual is:

    if is_eva and not C0.Config5.EVA:
      raise exception('RI')

    if not IsCoprocessor0Enabled():
      raise coprocessor_exception(0)

Add the missing checks.

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-04-20 19:49:40 +02:00
parent bcad139192
commit 84c2fdc397
1 changed files with 3 additions and 1 deletions
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4
target/mips/translate.c
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@ -20957,6 +20957,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_ld(ctx, OPC_LHUE, rt, rs, s);
break;
case NM_CACHEE:
check_eva(ctx);
check_cp0_enabled(ctx);
check_nms_dl_il_sl_tl_l2c(ctx);
gen_cache_operation(ctx, rt, rs, s);
break;
@ -24530,11 +24532,11 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
return;
case OPC_CACHEE:
check_eva(ctx);
check_cp0_enabled(ctx);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
/* Treat as NOP. */
return;
case OPC_PREFE:
check_cp0_enabled(ctx);