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PPC: Add some booke SPR defines

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The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.

Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2012-06-20 21:19:09 +02:00
parent 5025d5421d
commit 84755ed51e
1 changed files with 22 additions and 0 deletions
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22
target-ppc/cpu.h
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@ -1395,6 +1395,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
#define SPR_BOOKE_TLB1PS (0x159)
#define SPR_BOOKE_TLB2PS (0x15A)
#define SPR_BOOKE_TLB3PS (0x15B)
#define SPR_BOOKE_MAS7_MAS3 (0x174)
#define SPR_BOOKE_IVOR0 (0x190)
#define SPR_BOOKE_IVOR1 (0x191)
#define SPR_BOOKE_IVOR2 (0x192)
@ -1762,6 +1763,27 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
#define SPR_604_HID15 (0x3FF)
#define SPR_E500_SVR (0x3FF)
/* Disable MAS Interrupt Updates for Hypervisor */
#define EPCR_DMIUH (1 << 22)
/* Disable Guest TLB Management Instructions */
#define EPCR_DGTMI (1 << 23)
/* Guest Interrupt Computation Mode */
#define EPCR_GICM (1 << 24)
/* Interrupt Computation Mode */
#define EPCR_ICM (1 << 25)
/* Disable Embedded Hypervisor Debug */
#define EPCR_DUVD (1 << 26)
/* Instruction Storage Interrupt Directed to Guest State */
#define EPCR_ISIGS (1 << 27)
/* Data Storage Interrupt Directed to Guest State */
#define EPCR_DSIGS (1 << 28)
/* Instruction TLB Error Interrupt Directed to Guest State */
#define EPCR_ITLBGS (1 << 29)
/* Data TLB Error Interrupt Directed to Guest State */
#define EPCR_DTLBGS (1 << 30)
/* External Input Interrupt Directed to Guest State */
#define EPCR_EXTGS (1 << 31)
/*****************************************************************************/
/* PowerPC Instructions types definitions */
enum {