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hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs

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TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register on SUN6i based SoCs, we should lower interrupt when the guest
set this bit.

The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:

allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
...

Fix it.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
qianfan Zhao 2023-02-20 16:12:51 +08:00 committed by Peter Maydell
parent ff11422804
commit 8461bfdca9
2 changed files with 30 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
hw/i2c/allwinner-i2c.c
View File

@ -357,10 +357,16 @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
s->stat = STAT_FROM_STA(STAT_IDLE); s->stat = STAT_FROM_STA(STAT_IDLE);
s->cntr &= ~TWI_CNTR_M_STP; s->cntr &= ~TWI_CNTR_M_STP;
} }
if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
/* Interrupt flag cleared */ if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
/* Write 0 to clear this flag */
qemu_irq_lower(s->irq);
} else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
/* Write 1 to clear this flag */
s->cntr &= ~TWI_CNTR_INT_FLAG;
qemu_irq_lower(s->irq); qemu_irq_lower(s->irq);
} }
if ((s->cntr & TWI_CNTR_A_ACK) == 0) { if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) { if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
@ -451,9 +457,25 @@ static const TypeInfo allwinner_i2c_type_info = {
.class_init = allwinner_i2c_class_init, .class_init = allwinner_i2c_class_init,
}; };
static void allwinner_i2c_sun6i_init(Object *obj)
{
AWI2CState *s = AW_I2C(obj);
s->irq_clear_inverted = true;
}
static const TypeInfo allwinner_i2c_sun6i_type_info = {
.name = TYPE_AW_I2C_SUN6I,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AWI2CState),
.instance_init = allwinner_i2c_sun6i_init,
.class_init = allwinner_i2c_class_init,
};
static void allwinner_i2c_register_types(void) static void allwinner_i2c_register_types(void)
{ {
type_register_static(&allwinner_i2c_type_info); type_register_static(&allwinner_i2c_type_info);
type_register_static(&allwinner_i2c_sun6i_type_info);
} }
type_init(allwinner_i2c_register_types) type_init(allwinner_i2c_register_types)

6
include/hw/i2c/allwinner-i2c.h
View File

@ -28,6 +28,10 @@
#include "qom/object.h" #include "qom/object.h"
#define TYPE_AW_I2C "allwinner.i2c" #define TYPE_AW_I2C "allwinner.i2c"
/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i"
OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C) OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
#define AW_I2C_MEM_SIZE 0x24 #define AW_I2C_MEM_SIZE 0x24
@ -50,6 +54,8 @@ struct AWI2CState {
uint8_t srst; uint8_t srst;
uint8_t efr; uint8_t efr;
uint8_t lcr; uint8_t lcr;
bool irq_clear_inverted;
}; };
#endif /* ALLWINNER_I2C_H */ #endif /* ALLWINNER_I2C_H */