hw/pci: Add pcie_count_ds_port() and pcie_find_port_first() helpers
These two helpers enable host bridges to operate differently depending on the number of downstream ports, in particular if there is only a single port. Useful for CXL where HDM address decoders are allowed to be implicit in the host bridge if there is only a single root port. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230227153128.8164-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -161,6 +161,44 @@ PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn)
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return NULL;
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}
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/* Find first port in devfn number order */
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PCIDevice *pcie_find_port_first(PCIBus *bus)
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{
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int devfn;
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for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
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PCIDevice *d = bus->devices[devfn];
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if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
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continue;
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}
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if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
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return d;
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}
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}
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return NULL;
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}
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int pcie_count_ds_ports(PCIBus *bus)
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{
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int dsp_count = 0;
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int devfn;
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for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
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PCIDevice *d = bus->devices[devfn];
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if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
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continue;
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}
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if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
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dsp_count++;
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}
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}
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return dsp_count;
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}
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static bool pcie_slot_is_hotpluggbale_bus(HotplugHandler *plug_handler,
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BusState *bus)
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{
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@ -41,6 +41,8 @@ struct PCIEPort {
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void pcie_port_init_reg(PCIDevice *d);
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PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn);
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PCIDevice *pcie_find_port_first(PCIBus *bus);
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int pcie_count_ds_ports(PCIBus *bus);
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#define TYPE_PCIE_SLOT "pcie-slot"
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OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
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