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target-alpha: Cleanup MMU modes.

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Don't bother including executive and supervisor modes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2011-05-20 13:11:25 -07:00 committed by Richard Henderson
parent e52458fe29
commit 8417845ee9
2 changed files with 32 additions and 12 deletions
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37
target-alpha/cpu.h
View File

@ -317,9 +317,34 @@ enum {
IPR_LAST, IPR_LAST,
}; };
typedef struct CPUAlphaState CPUAlphaState; /* MMU modes definitions */
#define NB_MMU_MODES 4 /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
The Unix PALcode only exposes the kernel and user modes; presumably
executive and supervisor are used by VMS.
PALcode itself uses physical mode for code and kernel mode for data;
there are PALmode instructions that can access data via physical mode
or via an os-installed "alternate mode", which is one of the 4 above.
QEMU does not currently properly distinguish between code/data when
looking up addresses. To avoid having to address this issue, our
emulated PALcode will cheat and use the KSEG mapping for its code+data
rather than physical addresses.
Moreover, we're only emulating Unix PALcode, and not attempting VMS.
All of which allows us to drop all but kernel and user modes.
Elide the unused MMU modes to save space. */
#define NB_MMU_MODES 2
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
typedef struct CPUAlphaState CPUAlphaState;
struct CPUAlphaState { struct CPUAlphaState {
uint64_t ir[31]; uint64_t ir[31];
@ -370,15 +395,9 @@ struct CPUAlphaState {
#define cpu_gen_code cpu_alpha_gen_code #define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler #define cpu_signal_handler cpu_alpha_signal_handler
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _executive
#define MMU_MODE2_SUFFIX _supervisor
#define MMU_MODE3_SUFFIX _user
#define MMU_USER_IDX 3
static inline int cpu_mmu_index (CPUState *env) static inline int cpu_mmu_index (CPUState *env)
{ {
return (env->ps >> 3) & 3; return (env->ps >> 3) & 1;
} }
#include "cpu-all.h" #include "cpu-all.h"

7
target-alpha/translate.c
View File

@ -1522,8 +1522,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (palcode < 0x40) { if (palcode < 0x40) {
/* Privileged PAL code */ /* Privileged PAL code */
if (ctx->mem_idx & 1) if (ctx->mem_idx != MMU_KERNEL_IDX) {
goto invalid_opc; goto invalid_opc;
}
ret = gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); ret = gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);
} }
#endif #endif
@ -2651,11 +2652,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc; goto invalid_opc;
case 0xA: case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */ /* Longword virtual access with protection check (hw_ldl/w) */
tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_KERNEL_IDX);
break; break;
case 0xB: case 0xB:
/* Quadword virtual access with protection check (hw_ldq/w) */ /* Quadword virtual access with protection check (hw_ldq/w) */
tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_KERNEL_IDX);
break; break;
case 0xC: case 0xC:
/* Longword virtual access with alt access mode (hw_ldl/a)*/ /* Longword virtual access with alt access mode (hw_ldl/a)*/