tcg: Add and use TCG_OPF_64BIT.
This allows the simplification of the op_bits function from tcg/optimize.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson
Blue Swirl
parent
4b29ec41c8
commit
8399ad59e7
@ -92,81 +92,10 @@ static void reset_temp(TCGArg temp, int nb_temps, int nb_globals)
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}
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}
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static int op_bits(int op)
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static int op_bits(enum TCGOpcode op)
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{
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switch (op) {
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case INDEX_op_mov_i32:
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case INDEX_op_add_i32:
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case INDEX_op_sub_i32:
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case INDEX_op_mul_i32:
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case INDEX_op_and_i32:
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case INDEX_op_or_i32:
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case INDEX_op_xor_i32:
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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#ifdef TCG_TARGET_HAS_rot_i32
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case INDEX_op_rotl_i32:
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case INDEX_op_rotr_i32:
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#endif
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#ifdef TCG_TARGET_HAS_not_i32
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case INDEX_op_not_i32:
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#endif
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#ifdef TCG_TARGET_HAS_ext8s_i32
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case INDEX_op_ext8s_i32:
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#endif
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#ifdef TCG_TARGET_HAS_ext16s_i32
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case INDEX_op_ext16s_i32:
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#endif
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#ifdef TCG_TARGET_HAS_ext8u_i32
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case INDEX_op_ext8u_i32:
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#endif
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#ifdef TCG_TARGET_HAS_ext16u_i32
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case INDEX_op_ext16u_i32:
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#endif
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return 32;
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_mov_i64:
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case INDEX_op_add_i64:
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case INDEX_op_sub_i64:
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case INDEX_op_mul_i64:
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case INDEX_op_and_i64:
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case INDEX_op_or_i64:
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case INDEX_op_xor_i64:
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case INDEX_op_shl_i64:
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case INDEX_op_shr_i64:
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case INDEX_op_sar_i64:
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#ifdef TCG_TARGET_HAS_rot_i64
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case INDEX_op_rotl_i64:
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case INDEX_op_rotr_i64:
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#endif
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#ifdef TCG_TARGET_HAS_not_i64
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case INDEX_op_not_i64:
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#endif
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#ifdef TCG_TARGET_HAS_ext8s_i64
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case INDEX_op_ext8s_i64:
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#endif
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#ifdef TCG_TARGET_HAS_ext16s_i64
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case INDEX_op_ext16s_i64:
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#endif
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#ifdef TCG_TARGET_HAS_ext32s_i64
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case INDEX_op_ext32s_i64:
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#endif
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#ifdef TCG_TARGET_HAS_ext8u_i64
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case INDEX_op_ext8u_i64:
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#endif
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#ifdef TCG_TARGET_HAS_ext16u_i64
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case INDEX_op_ext16u_i64:
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#endif
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#ifdef TCG_TARGET_HAS_ext32u_i64
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case INDEX_op_ext32u_i64:
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#endif
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return 64;
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#endif
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default:
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fprintf(stderr, "Unrecognized operation %d in op_bits.\n", op);
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tcg_abort();
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}
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const TCGOpDef *def = &tcg_op_defs[op];
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return def->flags & TCG_OPF_64BIT ? 64 : 32;
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}
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static int op_to_movi(int op)
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@ -131,98 +131,98 @@ DEF(nor_i32, 1, 2, 0, 0)
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#endif
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#if TCG_TARGET_REG_BITS == 64
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DEF(mov_i64, 1, 1, 0, 0)
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DEF(movi_i64, 1, 0, 1, 0)
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DEF(setcond_i64, 1, 2, 1, 0)
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DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT)
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DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT)
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DEF(setcond_i64, 1, 2, 1, TCG_OPF_64BIT)
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/* load/store */
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DEF(ld8u_i64, 1, 1, 1, 0)
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DEF(ld8s_i64, 1, 1, 1, 0)
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DEF(ld16u_i64, 1, 1, 1, 0)
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DEF(ld16s_i64, 1, 1, 1, 0)
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DEF(ld32u_i64, 1, 1, 1, 0)
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DEF(ld32s_i64, 1, 1, 1, 0)
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DEF(ld_i64, 1, 1, 1, 0)
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DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(ld8u_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(ld8s_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(ld16u_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(ld16s_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(ld32u_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(ld32s_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(ld_i64, 1, 1, 1, TCG_OPF_64BIT)
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DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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/* arith */
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DEF(add_i64, 1, 2, 0, 0)
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DEF(sub_i64, 1, 2, 0, 0)
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DEF(mul_i64, 1, 2, 0, 0)
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DEF(add_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(sub_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(mul_i64, 1, 2, 0, TCG_OPF_64BIT)
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#ifdef TCG_TARGET_HAS_div_i64
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DEF(div_i64, 1, 2, 0, 0)
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DEF(divu_i64, 1, 2, 0, 0)
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DEF(rem_i64, 1, 2, 0, 0)
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DEF(remu_i64, 1, 2, 0, 0)
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DEF(div_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(divu_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(rem_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(remu_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_div2_i64
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DEF(div2_i64, 2, 3, 0, 0)
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DEF(divu2_i64, 2, 3, 0, 0)
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DEF(div2_i64, 2, 3, 0, TCG_OPF_64BIT)
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DEF(divu2_i64, 2, 3, 0, TCG_OPF_64BIT)
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#endif
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DEF(and_i64, 1, 2, 0, 0)
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DEF(or_i64, 1, 2, 0, 0)
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DEF(xor_i64, 1, 2, 0, 0)
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DEF(and_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(or_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(xor_i64, 1, 2, 0, TCG_OPF_64BIT)
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/* shifts/rotates */
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DEF(shl_i64, 1, 2, 0, 0)
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DEF(shr_i64, 1, 2, 0, 0)
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DEF(sar_i64, 1, 2, 0, 0)
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DEF(shl_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(shr_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(sar_i64, 1, 2, 0, TCG_OPF_64BIT)
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#ifdef TCG_TARGET_HAS_rot_i64
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DEF(rotl_i64, 1, 2, 0, 0)
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DEF(rotr_i64, 1, 2, 0, 0)
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DEF(rotl_i64, 1, 2, 0, TCG_OPF_64BIT)
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DEF(rotr_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_deposit_i64
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DEF(deposit_i64, 1, 2, 2, 0)
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DEF(deposit_i64, 1, 2, 2, TCG_OPF_64BIT)
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#endif
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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#ifdef TCG_TARGET_HAS_ext8s_i64
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DEF(ext8s_i64, 1, 1, 0, 0)
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DEF(ext8s_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_ext16s_i64
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DEF(ext16s_i64, 1, 1, 0, 0)
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DEF(ext16s_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_ext32s_i64
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DEF(ext32s_i64, 1, 1, 0, 0)
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DEF(ext32s_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_ext8u_i64
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DEF(ext8u_i64, 1, 1, 0, 0)
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DEF(ext8u_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_ext16u_i64
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DEF(ext16u_i64, 1, 1, 0, 0)
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DEF(ext16u_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_ext32u_i64
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DEF(ext32u_i64, 1, 1, 0, 0)
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DEF(ext32u_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_bswap16_i64
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DEF(bswap16_i64, 1, 1, 0, 0)
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DEF(bswap16_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_bswap32_i64
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DEF(bswap32_i64, 1, 1, 0, 0)
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DEF(bswap32_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_bswap64_i64
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DEF(bswap64_i64, 1, 1, 0, 0)
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DEF(bswap64_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_not_i64
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DEF(not_i64, 1, 1, 0, 0)
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DEF(not_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_neg_i64
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DEF(neg_i64, 1, 1, 0, 0)
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DEF(neg_i64, 1, 1, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_andc_i64
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DEF(andc_i64, 1, 2, 0, 0)
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DEF(andc_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_orc_i64
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DEF(orc_i64, 1, 2, 0, 0)
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DEF(orc_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_eqv_i64
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DEF(eqv_i64, 1, 2, 0, 0)
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DEF(eqv_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_nand_i64
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DEF(nand_i64, 1, 2, 0, 0)
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DEF(nand_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#ifdef TCG_TARGET_HAS_nor_i64
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DEF(nor_i64, 1, 2, 0, 0)
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DEF(nor_i64, 1, 2, 0, TCG_OPF_64BIT)
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#endif
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#endif
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@ -68,7 +68,7 @@ static void tcg_target_qemu_prologue(TCGContext *s);
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static void patch_reloc(uint8_t *code_ptr, int type,
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tcg_target_long value, tcg_target_long addend);
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static TCGOpDef tcg_op_defs[] = {
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TCGOpDef tcg_op_defs[] = {
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#define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
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#include "tcg-opc.h"
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#undef DEF
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21
tcg/tcg.h
21
tcg/tcg.h
@ -445,13 +445,18 @@ typedef struct TCGArgConstraint {
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#define TCG_MAX_OP_ARGS 16
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#define TCG_OPF_BB_END 0x01 /* instruction defines the end of a basic
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block */
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#define TCG_OPF_CALL_CLOBBER 0x02 /* instruction clobbers call registers
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and potentially update globals. */
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#define TCG_OPF_SIDE_EFFECTS 0x04 /* instruction has side effects : it
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cannot be removed if its output
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are not used */
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/* Bits for TCGOpDef->flags, 8 bits available. */
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enum {
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/* Instruction defines the end of a basic block. */
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TCG_OPF_BB_END = 0x01,
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/* Instruction clobbers call registers and potentially update globals. */
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TCG_OPF_CALL_CLOBBER = 0x02,
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/* Instruction has side effects: it cannot be removed
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if its outputs are not used. */
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TCG_OPF_SIDE_EFFECTS = 0x04,
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/* Instruction operands are 64-bits (otherwise 32-bits). */
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TCG_OPF_64BIT = 0x08,
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};
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typedef struct TCGOpDef {
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const char *name;
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@ -464,6 +469,8 @@ typedef struct TCGOpDef {
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#endif
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} TCGOpDef;
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extern TCGOpDef tcg_op_defs[];
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typedef struct TCGTargetOpDef {
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TCGOpcode op;
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const char *args_ct_str[TCG_MAX_OP_ARGS];
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