Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to the MemoryRegion valid.accepts callback. We'll need this for subpage_accepts(). We could take the approach we used with the read and write callbacks and add new a new _with_attrs version, but since there are so few implementations of the accepts hook we just change them all. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
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6d7b9a6c3b
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8372d38327
9
exec.c
9
exec.c
@ -2539,7 +2539,8 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
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}
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}
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static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
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static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return is_write;
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return is_write;
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}
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}
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@ -2762,7 +2763,8 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
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}
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}
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static bool subpage_accepts(void *opaque, hwaddr addr,
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static bool subpage_accepts(void *opaque, hwaddr addr,
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unsigned len, bool is_write)
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unsigned len, bool is_write,
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MemTxAttrs attrs)
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{
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{
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subpage_t *subpage = opaque;
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subpage_t *subpage = opaque;
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#if defined(DEBUG_SUBPAGE)
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#if defined(DEBUG_SUBPAGE)
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@ -2845,7 +2847,8 @@ static void readonly_mem_write(void *opaque, hwaddr addr,
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}
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}
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static bool readonly_mem_accepts(void *opaque, hwaddr addr,
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static bool readonly_mem_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return is_write;
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return is_write;
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}
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}
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@ -137,7 +137,8 @@ static void gsc_to_pci_forwarding(DinoState *s)
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}
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}
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static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
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static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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switch (addr) {
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switch (addr) {
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case DINO_IAR0:
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case DINO_IAR0:
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@ -420,14 +420,16 @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
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}
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}
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static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
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static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
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return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
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(size == 8 && addr == 0));
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(size == 8 && addr == 0));
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}
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}
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static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
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static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return addr == 0;
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return addr == 0;
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}
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}
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@ -439,7 +441,8 @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
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}
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}
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static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
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static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return is_write && size == 2;
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return is_write && size == 2;
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}
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}
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@ -458,7 +461,8 @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
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}
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}
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static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
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static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return (size == 1) || (is_write && size == 2);
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return (size == 1) || (is_write && size == 2);
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}
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}
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@ -564,7 +564,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
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}
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}
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static bool esp_mem_accepts(void *opaque, hwaddr addr,
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static bool esp_mem_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return (size == 1) || (is_write && size == 4);
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return (size == 1) || (is_write && size == 4);
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}
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}
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@ -498,7 +498,8 @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
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}
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}
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static bool pci_msix_accepts(void *opaque, hwaddr addr,
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static bool pci_msix_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return !(addr & (size - 1));
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return !(addr & (size - 1));
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}
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}
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@ -166,7 +166,8 @@ struct MemoryRegionOps {
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* as a machine check exception).
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* as a machine check exception).
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*/
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*/
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bool (*accepts)(void *opaque, hwaddr addr,
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bool (*accepts)(void *opaque, hwaddr addr,
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unsigned size, bool is_write);
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unsigned size, bool is_write,
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MemTxAttrs attrs);
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} valid;
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} valid;
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/* Internal implementation constraints: */
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/* Internal implementation constraints: */
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struct {
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struct {
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5
memory.c
5
memory.c
@ -1269,7 +1269,8 @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
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}
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}
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static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
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static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return false;
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return false;
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}
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}
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@ -1374,7 +1375,7 @@ bool memory_region_access_valid(MemoryRegion *mr,
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access_size = MAX(MIN(size, access_size_max), access_size_min);
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access_size = MAX(MIN(size, access_size_max), access_size_min);
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for (i = 0; i < size; i += access_size) {
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for (i = 0; i < size; i += access_size) {
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if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
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if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
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is_write)) {
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is_write, attrs)) {
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return false;
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return false;
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}
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}
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}
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}
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