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target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate

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Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2018-08-20 19:58:51 -07:00
parent 72d8ad67ba
commit 830bf10c82
2 changed files with 38 additions and 27 deletions
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40
target/s390x/mem_helper.c
View File

@ -1420,9 +1420,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
Int128 oldv; Int128 oldv;
bool fail; bool fail;
if (!HAVE_CMPXCHG128) { assert(HAVE_CMPXCHG128);
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
}
mem_idx = cpu_mmu_index(env, false); mem_idx = cpu_mmu_index(env, false);
oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
@ -2115,16 +2113,17 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr)
{ {
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
uint64_t hi, lo; uint64_t hi, lo;
int mem_idx;
TCGMemOpIdx oi;
Int128 v;
if (HAVE_ATOMIC128) { assert(HAVE_ATOMIC128);
int mem_idx = cpu_mmu_index(env, false);
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); mem_idx = cpu_mmu_index(env, false);
Int128 v = helper_atomic_ldo_be_mmu(env, addr, oi, ra); oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
hi = int128_gethi(v); v = helper_atomic_ldo_be_mmu(env, addr, oi, ra);
lo = int128_getlo(v); hi = int128_gethi(v);
} else { lo = int128_getlo(v);
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
}
env->retxl = lo; env->retxl = lo;
return hi; return hi;
@ -2145,15 +2144,16 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr,
uint64_t low, uint64_t high) uint64_t low, uint64_t high)
{ {
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
int mem_idx;
TCGMemOpIdx oi;
Int128 v;
if (HAVE_ATOMIC128) { assert(HAVE_ATOMIC128);
int mem_idx = cpu_mmu_index(env, false);
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); mem_idx = cpu_mmu_index(env, false);
Int128 v = int128_make128(low, high); oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
helper_atomic_sto_be_mmu(env, addr, v, oi, ra); v = int128_make128(low, high);
} else { helper_atomic_sto_be_mmu(env, addr, v, oi, ra);
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
}
} }
/* Execute instruction. This instruction executes an insn modified with /* Execute instruction. This instruction executes an insn modified with

25
target/s390x/translate.c
View File

@ -44,6 +44,7 @@
#include "trace-tcg.h" #include "trace-tcg.h"
#include "exec/translator.h" #include "exec/translator.h"
#include "exec/log.h" #include "exec/log.h"
#include "qemu/atomic128.h"
/* Information that (most) every instruction needs to manipulate. */ /* Information that (most) every instruction needs to manipulate. */
@ -2040,6 +2041,7 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
int r3 = get_field(s->fields, r3); int r3 = get_field(s->fields, r3);
int d2 = get_field(s->fields, d2); int d2 = get_field(s->fields, d2);
int b2 = get_field(s->fields, b2); int b2 = get_field(s->fields, b2);
DisasJumpType ret = DISAS_NEXT;
TCGv_i64 addr; TCGv_i64 addr;
TCGv_i32 t_r1, t_r3; TCGv_i32 t_r1, t_r3;
@ -2047,17 +2049,20 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
addr = get_address(s, 0, b2, d2); addr = get_address(s, 0, b2, d2);
t_r1 = tcg_const_i32(r1); t_r1 = tcg_const_i32(r1);
t_r3 = tcg_const_i32(r3); t_r3 = tcg_const_i32(r3);
if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
} else if (HAVE_CMPXCHG128) {
gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3);
} else { } else {
gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); gen_helper_exit_atomic(cpu_env);
ret = DISAS_NORETURN;
} }
tcg_temp_free_i64(addr); tcg_temp_free_i64(addr);
tcg_temp_free_i32(t_r1); tcg_temp_free_i32(t_r1);
tcg_temp_free_i32(t_r3); tcg_temp_free_i32(t_r3);
set_cc_static(s); set_cc_static(s);
return DISAS_NEXT; return ret;
} }
static DisasJumpType op_csst(DisasContext *s, DisasOps *o) static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
@ -3034,10 +3039,13 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
static DisasJumpType op_lpq(DisasContext *s, DisasOps *o) static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
{ {
if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_helper_lpq(o->out, cpu_env, o->in2);
} else if (HAVE_ATOMIC128) {
gen_helper_lpq_parallel(o->out, cpu_env, o->in2); gen_helper_lpq_parallel(o->out, cpu_env, o->in2);
} else { } else {
gen_helper_lpq(o->out, cpu_env, o->in2); gen_helper_exit_atomic(cpu_env);
return DISAS_NORETURN;
} }
return_low128(o->out2); return_low128(o->out2);
return DISAS_NEXT; return DISAS_NEXT;
@ -4414,10 +4422,13 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
{ {
if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
} else if (HAVE_ATOMIC128) {
gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out);
} else { } else {
gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); gen_helper_exit_atomic(cpu_env);
return DISAS_NORETURN;
} }
return DISAS_NEXT; return DISAS_NEXT;
} }