From 8280b12c0e4b515d707509dde4ddde05d9bda4ef Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 4 Nov 2014 15:37:17 +0000 Subject: [PATCH] target-mips: Make CP0.Config4 and CP0.Config5 registers signed Make the data type used for the CP0.Config4 and CP0.Config5 registers and their mask signed, for consistency with the remaining 32-bit CP0 registers, like CP0.Config0, etc. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c01bbdac2d..a08c2c8467 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -446,8 +446,8 @@ struct CPUMIPSState { #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 - uint32_t CP0_Config4; - uint32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 #define CP0C4_KScrExist 16 @@ -456,8 +456,8 @@ struct CPUMIPSState { #define CP0C4_FTLBWays 4 #define CP0C4_FTLBSets 0 #define CP0C4_MMUSizeExt 0 - uint32_t CP0_Config5; - uint32_t CP0_Config5_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31 #define CP0C5_K 30 #define CP0C5_CV 29