hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API
Switch the allwinner-a10-pit code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191008171740.9679-7-peter.maydell@linaro.org
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@ -22,7 +22,6 @@
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#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/timer/allwinner-a10-pit.h"
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#include "migration/vmstate.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/module.h"
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static void a10_pit_update_irq(AwA10PITState *s)
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static void a10_pit_update_irq(AwA10PITState *s)
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@ -80,6 +79,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
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return 0;
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return 0;
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}
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}
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/* Must be called inside a ptimer transaction block for s->timer[index] */
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static void a10_pit_set_freq(AwA10PITState *s, int index)
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static void a10_pit_set_freq(AwA10PITState *s, int index)
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{
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{
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uint32_t prescaler, source, source_freq;
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uint32_t prescaler, source, source_freq;
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@ -118,6 +118,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
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switch (offset & 0x0f) {
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switch (offset & 0x0f) {
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case AW_A10_PIT_TIMER_CONTROL:
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case AW_A10_PIT_TIMER_CONTROL:
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s->control[index] = value;
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s->control[index] = value;
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ptimer_transaction_begin(s->timer[index]);
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a10_pit_set_freq(s, index);
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a10_pit_set_freq(s, index);
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if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
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if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
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ptimer_set_count(s->timer[index], s->interval[index]);
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ptimer_set_count(s->timer[index], s->interval[index]);
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@ -131,10 +132,13 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
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} else {
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} else {
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ptimer_stop(s->timer[index]);
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ptimer_stop(s->timer[index]);
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}
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}
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ptimer_transaction_commit(s->timer[index]);
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break;
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break;
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case AW_A10_PIT_TIMER_INTERVAL:
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case AW_A10_PIT_TIMER_INTERVAL:
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s->interval[index] = value;
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s->interval[index] = value;
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ptimer_transaction_begin(s->timer[index]);
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ptimer_set_limit(s->timer[index], s->interval[index], 1);
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ptimer_set_limit(s->timer[index], s->interval[index], 1);
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ptimer_transaction_commit(s->timer[index]);
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break;
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break;
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case AW_A10_PIT_TIMER_COUNT:
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case AW_A10_PIT_TIMER_COUNT:
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s->count[index] = value;
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s->count[index] = value;
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@ -225,8 +229,10 @@ static void a10_pit_reset(DeviceState *dev)
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s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
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s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
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s->interval[i] = 0;
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s->interval[i] = 0;
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s->count[i] = 0;
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s->count[i] = 0;
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ptimer_transaction_begin(s->timer[i]);
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ptimer_stop(s->timer[i]);
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ptimer_stop(s->timer[i]);
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a10_pit_set_freq(s, i);
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a10_pit_set_freq(s, i);
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ptimer_transaction_commit(s->timer[i]);
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}
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}
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s->watch_dog_mode = 0;
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s->watch_dog_mode = 0;
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s->watch_dog_control = 0;
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s->watch_dog_control = 0;
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@ -255,7 +261,6 @@ static void a10_pit_init(Object *obj)
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{
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{
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AwA10PITState *s = AW_A10_PIT(obj);
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AwA10PITState *s = AW_A10_PIT(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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QEMUBH * bh[AW_A10_PIT_TIMER_NR];
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uint8_t i;
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uint8_t i;
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for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
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for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
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@ -270,8 +275,7 @@ static void a10_pit_init(Object *obj)
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tc->container = s;
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tc->container = s;
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tc->index = i;
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tc->index = i;
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bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
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s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT);
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s->timer[i] = ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT);
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}
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}
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}
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}
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