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tcg/riscv: Remove add with zero on user-only memory access

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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-08-05 07:38:14 -10:00
parent fa947a667f
commit 81c65ee223
1 changed files with 2 additions and 8 deletions
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10
tcg/riscv/tcg-target.c.inc
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@ -1130,10 +1130,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
tcg_out_ext32u(s, base, addr_regl); tcg_out_ext32u(s, base, addr_regl);
addr_regl = base; addr_regl = base;
} }
if (guest_base != 0) {
if (guest_base == 0) {
tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
} else {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
} }
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
@ -1199,10 +1196,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
tcg_out_ext32u(s, base, addr_regl); tcg_out_ext32u(s, base, addr_regl);
addr_regl = base; addr_regl = base;
} }
if (guest_base != 0) {
if (guest_base == 0) {
tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
} else {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
} }
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);