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x86 and machine queue, 2019-10-23

Browse Source 
Features:
 * Denverton CPU model (Tao Xu)
 
 Cleanups:
 * Eliminate remaining places that abuse
   memory_region_allocate_system_memory() (Igor Mammedov)
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Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

x86 and machine queue, 2019-10-23

Features:
* Denverton CPU model (Tao Xu)

Cleanups:
* Eliminate remaining places that abuse
  memory_region_allocate_system_memory() (Igor Mammedov)

# gpg: Signature made Thu 24 Oct 2019 03:45:34 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request:
  hppa: drop usage of memory_region_allocate_system_memory() for ROM
  ppc: rs6000_mc: drop usage of memory_region_allocate_system_memory()
  sparc64: use memory_region_allocate_system_memory() only for '-m' specified RAM
  target/i386: Introduce Denverton CPU model

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-10-24 10:43:20 +01:00
commit 81c1f71eeb
4 changed files with 72 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
hw/hppa/machine.c
View File

@ -161,9 +161,8 @@ static void machine_hppa_init(MachineState *machine)
g_free(firmware_filename);
rom_region = g_new(MemoryRegion, 1);
memory_region_allocate_system_memory(rom_region, OBJECT(machine),
"firmware",
(FIRMWARE_END - FIRMWARE_START));
memory_region_init_ram(rom_region, NULL, "firmware",
(FIRMWARE_END - FIRMWARE_START), &error_fatal);
memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region);
/* Load kernel */

15
hw/ppc/rs6000_mc.c
View File

@ -144,6 +144,7 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
RS6000MCState *s = RS6000MC_DEVICE(dev);
int socket = 0;
unsigned int ram_size = s->ram_size / MiB;
Error *local_err = NULL;
while (socket < 6) {
if (ram_size >= 64) {
@ -165,19 +166,21 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
if (s->simm_size[socket]) {
char name[] = "simm.?";
name[5] = socket + '0';
memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
name,
s->simm_size[socket] * MiB);
memory_region_init_ram(&s->simm[socket], OBJECT(dev), name,
s->simm_size[socket] * MiB, &local_err);
if (local_err) {
goto out;
}
memory_region_add_subregion_overlap(get_system_memory(), 0,
&s->simm[socket], socket);
}
}
if (ram_size) {
/* unable to push all requested RAM in SIMMs */
error_setg(errp, "RAM size incompatible with this board. "
error_setg(&local_err, "RAM size incompatible with this board. "
"Try again with something else, like %" PRId64 " MB",
s->ram_size / MiB - ram_size);
return;
goto out;
}
if (s->autoconfigure) {
@ -193,6 +196,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
rs6000mc_port_list, s, "rs6000mc");
out:
error_propagate(errp, local_err);
}
static const VMStateDescription vmstate_rs6000mc = {

25
hw/sparc64/niagara.c
View File

@ -36,6 +36,7 @@
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"
#include "qapi/error.h"
typedef struct NiagaraBoardState {
MemoryRegion hv_ram;
@ -106,8 +107,8 @@ static void niagara_init(MachineState *machine)
/* init CPUs */
sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE);
/* set up devices */
memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
NIAGARA_HV_RAM_SIZE);
memory_region_init_ram(&s->hv_ram, NULL, "sun4v-hv.ram",
NIAGARA_HV_RAM_SIZE, &error_fatal);
memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);
memory_region_allocate_system_memory(&s->partition_ram, NULL,
@ -116,17 +117,17 @@ static void niagara_init(MachineState *machine)
memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
&s->partition_ram);
memory_region_allocate_system_memory(&s->nvram, NULL,
"sun4v.nvram", NIAGARA_NVRAM_SIZE);
memory_region_init_ram(&s->nvram, NULL, "sun4v.nvram", NIAGARA_NVRAM_SIZE,
&error_fatal);
memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
memory_region_allocate_system_memory(&s->md_rom, NULL,
"sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
memory_region_init_ram(&s->md_rom, NULL, "sun4v-md.rom",
NIAGARA_MD_ROM_SIZE, &error_fatal);
memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
memory_region_allocate_system_memory(&s->hv_rom, NULL,
"sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
memory_region_init_ram(&s->hv_rom, NULL, "sun4v-hv.rom",
NIAGARA_HV_ROM_SIZE, &error_fatal);
memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
memory_region_allocate_system_memory(&s->prom, NULL,
"sun4v.prom", PROM_SIZE_MAX);
memory_region_init_ram(&s->prom, NULL, "sun4v.prom", PROM_SIZE_MAX,
&error_fatal);
memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);
add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE);
@ -143,8 +144,8 @@ static void niagara_init(MachineState *machine)
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
int size = blk_getlength(blk);
if (size > 0) {
memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
"sun4v_vdisk.ram", size);
memory_region_init_ram(&s->vdisk_ram, NULL, "sun4v_vdisk.ram", size,
&error_fatal);
memory_region_add_subregion(get_system_memory(),
NIAGARA_VDISK_BASE, &s->vdisk_ram);
dinfo->is_default = 1;

47
target/i386/cpu.c
View File

@ -2724,6 +2724,53 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
},
{
.name = "Denverton",
.level = 21,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 95,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
CPUID_SSE | CPUID_SSE2,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
CPUID_7_0_EDX_SPEC_CTRL_SSBD,
/*
* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.features[FEAT_ARCH_CAPABILITIES] =
MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
.xlevel = 0x80000008,
.model_id = "Intel Atom Processor (Denverton)",
},
{
.name = "Snowridge",
.level = 27,