mirror of https://gitlab.com/qemu-project/qemu
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and "s->cfg_ptr->vlen >> 3". Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240122161107.26737-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
Alistair Francis
parent
33383193c8
commit
81b9ef995a
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@ -217,7 +217,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
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/* vector register offset from env */
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static uint32_t vreg_ofs(DisasContext *s, int reg)
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{
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return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8;
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return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlenb;
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}
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/* check functions */
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@ -627,11 +627,11 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
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* As simd_desc supports at most 2048 bytes, and in this implementation,
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* the max vector group length is 4096 bytes. So split it into two parts.
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*
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* The first part is vlen in bytes, encoded in maxsz of simd_desc.
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* The first part is vlen in bytes (vlenb), encoded in maxsz of simd_desc.
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* The second part is lmul, encoded in data of simd_desc.
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*/
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
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@ -791,8 +791,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
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mask = tcg_temp_new_ptr();
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base = get_gpr(s, rs1, EXT_NONE);
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stride = get_gpr(s, rs2, EXT_NONE);
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
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@ -897,8 +897,8 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
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mask = tcg_temp_new_ptr();
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index = tcg_temp_new_ptr();
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base = get_gpr(s, rs1, EXT_NONE);
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
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@ -1036,8 +1036,8 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
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dest = tcg_temp_new_ptr();
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mask = tcg_temp_new_ptr();
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base = get_gpr(s, rs1, EXT_NONE);
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
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@ -1086,7 +1086,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
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uint32_t width, gen_helper_ldst_whole *fn,
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DisasContext *s, bool is_store)
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{
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uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
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uint32_t evl = s->cfg_ptr->vlenb * nf / width;
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
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@ -1096,8 +1096,8 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
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uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
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dest = tcg_temp_new_ptr();
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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base = get_gpr(s, rs1, EXT_NONE);
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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@ -1199,8 +1199,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
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tcg_env, s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data, fn);
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tcg_env, s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data, fn);
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}
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mark_vs_dirty(s);
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gen_set_label(over);
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@ -1248,8 +1248,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
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data = FIELD_DP32(data, VDATA, VTA, s->vta);
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
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@ -1410,8 +1410,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
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data = FIELD_DP32(data, VDATA, VTA, s->vta);
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
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@ -1492,8 +1492,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs1),
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vreg_ofs(s, a->rs2),
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tcg_env, s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8,
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tcg_env, s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb,
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data, fn);
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mark_vs_dirty(s);
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gen_set_label(over);
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@ -1568,8 +1568,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs1),
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vreg_ofs(s, a->rs2),
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tcg_env, s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data, fn);
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tcg_env, s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data, fn);
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mark_vs_dirty(s);
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gen_set_label(over);
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return true;
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@ -1639,8 +1639,8 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
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vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data, fn);
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vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data, fn);
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mark_vs_dirty(s);
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gen_set_label(over);
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return true;
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@ -1831,8 +1831,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2036,8 +2036,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
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tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
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tcg_env, s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data,
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tcg_env, s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data,
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fns[s->sew]);
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gen_set_label(over);
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}
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@ -2082,8 +2082,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
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};
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tcg_gen_ext_tl_i64(s1_i64, s1);
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
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fns[s->sew](dest, s1_i64, tcg_env, desc);
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}
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@ -2121,8 +2121,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
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s1 = tcg_constant_i64(simm);
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dest = tcg_temp_new_ptr();
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
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fns[s->sew](dest, s1, tcg_env, desc);
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@ -2275,8 +2275,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew - 1]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2303,8 +2303,8 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
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dest = tcg_temp_new_ptr();
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mask = tcg_temp_new_ptr();
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src2 = tcg_temp_new_ptr();
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
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@ -2391,8 +2391,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew - 1]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2465,8 +2465,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew - 1]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2581,8 +2581,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs2), tcg_env,
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s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data, fn);
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s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data, fn);
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mark_vs_dirty(s);
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gen_set_label(over);
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return true;
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@ -2691,8 +2691,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
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do_nanbox(s, t1, cpu_fpr[a->rs1]);
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dest = tcg_temp_new_ptr();
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
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s->cfg_ptr->vlen / 8, data));
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
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fns[s->sew - 1](dest, t1, tcg_env, desc);
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@ -2770,8 +2770,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew - 1]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2821,8 +2821,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2888,8 +2888,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
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s->cfg_ptr->vlenb, data, \
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fns[s->sew - 1]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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@ -2937,8 +2937,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), tcg_env, \
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s->cfg_ptr->vlen / 8, \
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s->cfg_ptr->vlen / 8, data, \
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s->cfg_ptr->vlenb, \
|
||||
s->cfg_ptr->vlenb, data, \
|
||||
fns[s->sew]); \
|
||||
mark_vs_dirty(s); \
|
||||
gen_set_label(over); \
|
||||
|
|
@ -3027,8 +3027,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
|
|||
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
|
||||
vreg_ofs(s, a->rs1), \
|
||||
vreg_ofs(s, a->rs2), tcg_env, \
|
||||
s->cfg_ptr->vlen / 8, \
|
||||
s->cfg_ptr->vlen / 8, data, fn); \
|
||||
s->cfg_ptr->vlenb, \
|
||||
s->cfg_ptr->vlenb, data, fn); \
|
||||
mark_vs_dirty(s); \
|
||||
gen_set_label(over); \
|
||||
return true; \
|
||||
|
|
@ -3061,8 +3061,8 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
|
|||
mask = tcg_temp_new_ptr();
|
||||
src2 = tcg_temp_new_ptr();
|
||||
dst = dest_gpr(s, a->rd);
|
||||
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
|
||||
s->cfg_ptr->vlen / 8, data));
|
||||
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
|
||||
s->cfg_ptr->vlenb, data));
|
||||
|
||||
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
|
||||
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
|
||||
|
|
@ -3090,8 +3090,8 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
|
|||
mask = tcg_temp_new_ptr();
|
||||
src2 = tcg_temp_new_ptr();
|
||||
dst = dest_gpr(s, a->rd);
|
||||
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
|
||||
s->cfg_ptr->vlen / 8, data));
|
||||
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
|
||||
s->cfg_ptr->vlenb, data));
|
||||
|
||||
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
|
||||
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
|
||||
|
|
@ -3128,8 +3128,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
|
|||
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
|
||||
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
|
||||
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
|
||||
tcg_env, s->cfg_ptr->vlen / 8, \
|
||||
s->cfg_ptr->vlen / 8, \
|
||||
tcg_env, s->cfg_ptr->vlenb, \
|
||||
s->cfg_ptr->vlenb, \
|
||||
data, fn); \
|
||||
mark_vs_dirty(s); \
|
||||
gen_set_label(over); \
|
||||
|
|
@ -3171,8 +3171,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
|
|||
};
|
||||
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
|
||||
vreg_ofs(s, a->rs2), tcg_env,
|
||||
s->cfg_ptr->vlen / 8,
|
||||
s->cfg_ptr->vlen / 8, data, fns[s->sew]);
|
||||
s->cfg_ptr->vlenb,
|
||||
s->cfg_ptr->vlenb, data, fns[s->sew]);
|
||||
mark_vs_dirty(s);
|
||||
gen_set_label(over);
|
||||
return true;
|
||||
|
|
@ -3200,8 +3200,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
|
|||
gen_helper_vid_v_w, gen_helper_vid_v_d,
|
||||
};
|
||||
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
|
||||
tcg_env, s->cfg_ptr->vlen / 8,
|
||||
s->cfg_ptr->vlen / 8,
|
||||
tcg_env, s->cfg_ptr->vlenb,
|
||||
s->cfg_ptr->vlenb,
|
||||
data, fns[s->sew]);
|
||||
mark_vs_dirty(s);
|
||||
gen_set_label(over);
|
||||
|
|
@ -3620,8 +3620,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
|
|||
data = FIELD_DP32(data, VDATA, VTA, s->vta);
|
||||
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
|
||||
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
|
||||
tcg_env, s->cfg_ptr->vlen / 8,
|
||||
s->cfg_ptr->vlen / 8, data,
|
||||
tcg_env, s->cfg_ptr->vlenb,
|
||||
s->cfg_ptr->vlenb, data,
|
||||
fns[s->sew]);
|
||||
mark_vs_dirty(s);
|
||||
gen_set_label(over);
|
||||
|
|
@ -3641,7 +3641,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
|
|||
vext_check_isa_ill(s) && \
|
||||
QEMU_IS_ALIGNED(a->rd, LEN) && \
|
||||
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
|
||||
uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
|
||||
uint32_t maxsz = s->cfg_ptr->vlenb * LEN; \
|
||||
if (s->vstart_eq_zero) { \
|
||||
tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
|
||||
vreg_ofs(s, a->rs2), maxsz, maxsz); \
|
||||
|
|
@ -3723,8 +3723,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
|
|||
|
||||
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
|
||||
vreg_ofs(s, a->rs2), tcg_env,
|
||||
s->cfg_ptr->vlen / 8,
|
||||
s->cfg_ptr->vlen / 8, data, fn);
|
||||
s->cfg_ptr->vlenb,
|
||||
s->cfg_ptr->vlenb, data, fn);
|
||||
|
||||
mark_vs_dirty(s);
|
||||
gen_set_label(over);
|
||||
|
|
|
|||
Loading…
Reference in New Issue