mirror of https://gitlab.com/qemu-project/qemu
target-arm: Register EL3 versions of ELR and SPSR
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-17-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2114,6 +2114,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
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{ .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_NO_MIGRATE,
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.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
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.access = PL3_RW,
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.fieldoffset = offsetof(CPUARMState, elr_el[3]) },
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{ .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_NO_MIGRATE,
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.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
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.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
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REGINFO_SENTINEL
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};
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static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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uint64_t value)
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{
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{
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@ -2368,6 +2381,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
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define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_MPU)) {
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if (arm_feature(env, ARM_FEATURE_MPU)) {
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/* These are the MPU registers prior to PMSAv6. Any new
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/* These are the MPU registers prior to PMSAv6. Any new
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* PMSA core later than the ARM946 will require that we
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* PMSA core later than the ARM946 will require that we
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