hw/isa/piix4: Rename reset control operations to match PIIX3
Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-18-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -148,8 +148,8 @@ static void piix4_request_i8259_irq(void *opaque, int irq, int level)
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qemu_set_irq(s->cpu_intr, level);
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}
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static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int len)
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static void rcr_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int len)
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{
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PIIX4State *s = opaque;
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@ -161,16 +161,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
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s->rcr = val & 2; /* keep System Reset type only */
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}
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static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
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static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len)
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{
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PIIX4State *s = opaque;
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return s->rcr;
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}
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static const MemoryRegionOps piix4_rcr_ops = {
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.read = piix4_rcr_read,
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.write = piix4_rcr_write,
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static const MemoryRegionOps rcr_ops = {
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.read = rcr_read,
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.write = rcr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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@ -194,7 +194,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
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qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
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"intr", 1);
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memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
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memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s,
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"reset-control", 1);
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memory_region_add_subregion_overlap(pci_address_space_io(dev),
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PIIX_RCR_IOPORT, &s->rcr_mem, 1);
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