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target/ppc: Improve timebase register defines naming

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The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.

The ISA changed around v2.03 to bring TB and TBU reads into the SPR
space at 268 and 269 (access via mftb TBR-space is still supported
but will be phased out). Later, VTB was added which is an entirely
different register.

The SPR number defines in QEMU are understandably inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-09-13 14:24:08 +10:00
parent 19e81ce51e
commit 80e28a4147
2 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/ppc/cpu.h
View File

@ -1750,8 +1750,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_USPRG5 (0x105) #define SPR_USPRG5 (0x105)
#define SPR_USPRG6 (0x106) #define SPR_USPRG6 (0x106)
#define SPR_USPRG7 (0x107) #define SPR_USPRG7 (0x107)
#define SPR_VTBL (0x10C) #define SPR_TBL (0x10C)
#define SPR_VTBU (0x10D) #define SPR_TBU (0x10D)
#define SPR_SPRG0 (0x110) #define SPR_SPRG0 (0x110)
#define SPR_SPRG1 (0x111) #define SPR_SPRG1 (0x111)
#define SPR_SPRG2 (0x112) #define SPR_SPRG2 (0x112)
@ -1764,8 +1764,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_SPRG7 (0x117) #define SPR_SPRG7 (0x117)
#define SPR_ASR (0x118) #define SPR_ASR (0x118)
#define SPR_EAR (0x11A) #define SPR_EAR (0x11A)
#define SPR_TBL (0x11C) #define SPR_WR_TBL (0x11C)
#define SPR_TBU (0x11D) #define SPR_WR_TBU (0x11D)
#define SPR_TBU40 (0x11E) #define SPR_TBU40 (0x11E)
#define SPR_SVR (0x11E) #define SPR_SVR (0x11E)
#define SPR_BOOKE_PIR (0x11E) #define SPR_BOOKE_PIR (0x11E)

10
target/ppc/helper_regs.c
View File

@ -461,22 +461,22 @@ void register_generic_sprs(PowerPCCPU *cpu)
/* Time base */ /* Time base */
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
spr_register(env, SPR_VTBL, "TB", spr_register(env, SPR_TBL, "TB",
#else #else
spr_register(env, SPR_VTBL, "TBL", spr_register(env, SPR_TBL, "TBL",
#endif #endif
&spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, SPR_NOACCESS,
0x00000000); 0x00000000);
spr_register(env, SPR_TBL, "TBL", spr_register(env, SPR_WR_TBL, "TBL",
&spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, &spr_write_tbl, &spr_read_tbl, &spr_write_tbl,
0x00000000); 0x00000000);
spr_register(env, SPR_VTBU, "TBU", spr_register(env, SPR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS, &spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS, &spr_read_tbu, SPR_NOACCESS,
0x00000000); 0x00000000);
spr_register(env, SPR_TBU, "TBU", spr_register(env, SPR_WR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS, &spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, &spr_write_tbu, &spr_read_tbu, &spr_write_tbu,
0x00000000); 0x00000000);