Implement sun4u PCI IRQ routing.
Allow multiple PCI busses and PCI-PCI bridges. Fix bugs in Versatile PCI implementation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2166 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
d2b5931756
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37
hw/apb_pci.c
37
hw/apb_pci.c
@ -21,6 +21,11 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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* THE SOFTWARE.
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*/
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*/
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/* XXX This file and most of its contests are somewhat misnamed. The
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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#include "vl.h"
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#include "vl.h"
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typedef target_phys_addr_t pci_addr_t;
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
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#include "pci_host.h"
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@ -179,17 +184,25 @@ static CPUReadMemoryFunc *pci_apb_ioread[] = {
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&pci_apb_ioreadl,
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&pci_apb_ioreadl,
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};
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};
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/* The APB host has an IRQ line for each IRQ line of each slot. */
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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{
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/* ??? As mentioned below this is probably wrong. */
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return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
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return irq_num;
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}
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static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int bus_offset;
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if (pci_dev->devfn & 1)
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bus_offset = 16;
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else
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bus_offset = 0;
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return bus_offset + irq_num;
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}
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}
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static void pci_apb_set_irq(void *pic, int irq_num, int level)
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static void pci_apb_set_irq(void *pic, int irq_num, int level)
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{
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{
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/* ??? This is almost certainly wrong. However the rest of the sun4u
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/* PCI IRQ map onto the first 32 INO. */
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IRQ handling is missing, as is OpenBIOS support, so it wouldn't work
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anyway. */
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pic_set_irq_new(pic, irq_num, level);
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pic_set_irq_new(pic, irq_num, level);
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}
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}
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@ -199,10 +212,12 @@ PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
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APBState *s;
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APBState *s;
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PCIDevice *d;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
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PCIDevice *apb;
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PCIBus *secondary;
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s = qemu_mallocz(sizeof(APBState));
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s = qemu_mallocz(sizeof(APBState));
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/* Ultrasparc APB main bus */
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/* Ultrasparc PBM main bus */
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s->bus = pci_register_bus(pci_apb_set_irq, pci_apb_map_irq, pic, 0);
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s->bus = pci_register_bus(pci_apb_set_irq, pci_pbm_map_irq, pic, 0, 32);
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pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
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pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
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pci_apb_config_write, s);
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pci_apb_config_write, s);
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@ -219,7 +234,7 @@ PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
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cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
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cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
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d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
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d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
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-1, NULL, NULL);
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0, NULL, NULL);
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d->config[0x00] = 0x8e; // vendor_id : Sun
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d->config[0x00] = 0x8e; // vendor_id : Sun
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d->config[0x01] = 0x10;
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x00; // device_id
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d->config[0x02] = 0x00; // device_id
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@ -234,7 +249,11 @@ PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
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d->config[0x0B] = 0x06; // class_base = PCI_bridge
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d->config[0x0B] = 0x06; // class_base = PCI_bridge
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x0E] = 0x00; // header_type
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d->config[0x0E] = 0x00; // header_type
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return s->bus;
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/* APB secondary busses */
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secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq);
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pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq);
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return secondary;
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}
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}
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@ -92,7 +92,8 @@ PCIBus *pci_grackle_init(uint32_t base, void *pic)
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int pci_mem_config, pci_mem_data;
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int pci_mem_config, pci_mem_data;
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s = qemu_mallocz(sizeof(GrackleState));
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s = qemu_mallocz(sizeof(GrackleState));
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s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq, pic, 0);
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s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,
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pic, 0, 0);
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pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
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pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
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pci_grackle_config_write, s);
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pci_grackle_config_write, s);
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103
hw/pci.c
103
hw/pci.c
@ -35,9 +35,11 @@ struct PCIBus {
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SetIRQFunc *low_set_irq;
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SetIRQFunc *low_set_irq;
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void *irq_opaque;
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *devices[256];
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PCIDevice *parent_dev;
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PCIBus *next;
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/* The bus IRQ state is the logical OR of the connected devices.
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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Keep a count of the number of devices with raised IRQs. */
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int irq_count[4];
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int irq_count[];
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};
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};
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static void pci_update_mappings(PCIDevice *d);
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static void pci_update_mappings(PCIDevice *d);
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@ -47,19 +49,29 @@ static int pci_irq_index;
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static PCIBus *first_bus;
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static PCIBus *first_bus;
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *pic, int devfn_min)
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void *pic, int devfn_min, int nirq)
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{
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{
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PCIBus *bus;
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PCIBus *bus;
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bus = qemu_mallocz(sizeof(PCIBus));
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bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
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bus->set_irq = set_irq;
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bus->set_irq = set_irq;
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bus->map_irq = map_irq;
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bus->map_irq = map_irq;
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bus->irq_opaque = pic;
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bus->irq_opaque = pic;
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bus->devfn_min = devfn_min;
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bus->devfn_min = devfn_min;
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memset(bus->irq_count, 0, sizeof(bus->irq_count));
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first_bus = bus;
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first_bus = bus;
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return bus;
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return bus;
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}
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}
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PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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{
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PCIBus *bus;
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bus = qemu_mallocz(sizeof(PCIBus));
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bus->map_irq = map_irq;
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bus->parent_dev = dev;
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bus->next = dev->bus->next;
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dev->bus->next = bus;
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return bus;
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}
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int pci_bus_num(PCIBus *s)
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int pci_bus_num(PCIBus *s)
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{
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{
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return s->bus_num;
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return s->bus_num;
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@ -351,7 +363,9 @@ void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
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addr, val, len);
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addr, val, len);
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#endif
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#endif
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bus_num = (addr >> 16) & 0xff;
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bus_num = (addr >> 16) & 0xff;
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if (bus_num != 0)
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while (s && s->bus_num != bus_num)
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s = s->next;
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if (!s)
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return;
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return;
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pci_dev = s->devices[(addr >> 8) & 0xff];
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pci_dev = s->devices[(addr >> 8) & 0xff];
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if (!pci_dev)
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if (!pci_dev)
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@ -372,7 +386,9 @@ uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
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uint32_t val;
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uint32_t val;
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bus_num = (addr >> 16) & 0xff;
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bus_num = (addr >> 16) & 0xff;
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if (bus_num != 0)
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while (s && s->bus_num != bus_num)
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s= s->next;
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if (!s)
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goto fail;
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goto fail;
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pci_dev = s->devices[(addr >> 8) & 0xff];
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pci_dev = s->devices[(addr >> 8) & 0xff];
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if (!pci_dev) {
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if (!pci_dev) {
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@ -411,11 +427,21 @@ uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
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/* 0 <= irq_num <= 3. level must be 0 or 1 */
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/* 0 <= irq_num <= 3. level must be 0 or 1 */
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void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
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void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
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{
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{
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PCIBus *bus = pci_dev->bus;
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PCIBus *bus;
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int change;
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change = level - pci_dev->irq_state[irq_num];
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if (!change)
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return;
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irq_num = bus->map_irq(pci_dev, irq_num);
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bus->irq_count[irq_num] += level - pci_dev->irq_state[irq_num];
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pci_dev->irq_state[irq_num] = level;
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pci_dev->irq_state[irq_num] = level;
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bus = pci_dev->bus;
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while (!bus->set_irq) {
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irq_num = bus->map_irq(pci_dev, irq_num);
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pci_dev = bus->parent_dev;
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bus = pci_dev->bus;
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}
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bus->irq_count[irq_num] += change;
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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}
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}
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@ -465,6 +491,9 @@ static void pci_info_device(PCIDevice *d)
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if (d->config[PCI_INTERRUPT_PIN] != 0) {
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if (d->config[PCI_INTERRUPT_PIN] != 0) {
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term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
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term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
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}
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}
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if (class == 0x0604) {
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term_printf(" BUS %d.\n", d->config[0x19]);
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}
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for(i = 0;i < PCI_NUM_REGIONS; i++) {
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for(i = 0;i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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r = &d->io_regions[i];
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if (r->size != 0) {
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if (r->size != 0) {
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@ -478,14 +507,19 @@ static void pci_info_device(PCIDevice *d)
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}
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}
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}
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}
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}
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}
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if (class == 0x0604 && d->config[0x19] != 0) {
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pci_for_each_device(d->config[0x19], pci_info_device);
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}
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}
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}
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void pci_for_each_device(void (*fn)(PCIDevice *d))
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void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
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{
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{
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PCIBus *bus = first_bus;
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PCIBus *bus = first_bus;
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PCIDevice *d;
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PCIDevice *d;
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int devfn;
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int devfn;
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while (bus && bus->bus_num != bus_num)
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bus = bus->next;
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if (bus) {
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if (bus) {
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for(devfn = 0; devfn < 256; devfn++) {
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for(devfn = 0; devfn < 256; devfn++) {
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d = bus->devices[devfn];
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d = bus->devices[devfn];
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@ -497,7 +531,7 @@ void pci_for_each_device(void (*fn)(PCIDevice *d))
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void pci_info(void)
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void pci_info(void)
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{
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{
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pci_for_each_device(pci_info_device);
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pci_for_each_device(0, pci_info_device);
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}
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}
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/* Initialize a PCI NIC. */
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/* Initialize a PCI NIC. */
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@ -515,3 +549,50 @@ void pci_nic_init(PCIBus *bus, NICInfo *nd)
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}
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}
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}
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}
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typedef struct {
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PCIDevice dev;
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PCIBus *bus;
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} PCIBridge;
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void pci_bridge_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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PCIBridge *s = (PCIBridge *)d;
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if (address == 0x19 || (address == 0x18 && len > 1)) {
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if (address == 0x19)
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s->bus->bus_num = val & 0xff;
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else
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s->bus->bus_num = (val >> 8) & 0xff;
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#if defined(DEBUG_PCI)
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printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
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#endif
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}
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pci_default_write_config(d, address, val, len);
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}
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PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
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pci_map_irq_fn map_irq, const char *name)
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{
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PCIBridge *s;
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s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
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devfn, NULL, pci_bridge_write_config);
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s->dev.config[0x00] = id >> 16;
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s->dev.config[0x01] = id > 24;
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s->dev.config[0x02] = id; // device_id
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s->dev.config[0x03] = id >> 8;
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s->dev.config[0x04] = 0x06; // command = bus master, pci mem
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s->dev.config[0x05] = 0x00;
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s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
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s->dev.config[0x07] = 0x00; // status = fast devsel
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s->dev.config[0x08] = 0x00; // revision
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s->dev.config[0x09] = 0x00; // programming i/f
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s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
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s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
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s->dev.config[0x0D] = 0x10; // latency_timer
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s->dev.config[0x0E] = 0x81; // header_type
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s->dev.config[0x1E] = 0xa0; // secondary status
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s->bus = pci_register_secondary_bus(&s->dev, map_irq);
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return s->bus;
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}
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@ -59,7 +59,7 @@ PCIBus *i440fx_init(void)
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I440FXState *s;
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I440FXState *s;
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s = qemu_mallocz(sizeof(I440FXState));
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s = qemu_mallocz(sizeof(I440FXState));
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b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, NULL, 0);
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b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, NULL, 0, 4);
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s->bus = b;
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s->bus = b;
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register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
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register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
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@ -226,6 +226,7 @@ static uint32_t pci_bios_io_addr;
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static uint32_t pci_bios_mem_addr;
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static uint32_t pci_bios_mem_addr;
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/* host irqs corresponding to PCI irqs A-D */
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/* host irqs corresponding to PCI irqs A-D */
|
||||||
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
|
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
|
||||||
|
static int pci_bios_next_bus;
|
||||||
|
|
||||||
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
|
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
|
||||||
{
|
{
|
||||||
@ -320,6 +321,14 @@ static void pci_bios_init_device(PCIDevice *d)
|
|||||||
pci_set_io_region_addr(d, 3, 0x374);
|
pci_set_io_region_addr(d, 3, 0x374);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
case 0x0604:
|
||||||
|
/* PCI to PCI bridge. Assign bus ID and recurse to configure
|
||||||
|
devices on the secondary bus. */
|
||||||
|
i = pci_bios_next_bus++;
|
||||||
|
pci_config_writeb(d, 0x18, pci_bus_num(d->bus));
|
||||||
|
pci_config_writeb(d, 0x19, i);
|
||||||
|
pci_for_each_device(i, pci_bios_init_device);
|
||||||
|
break;
|
||||||
case 0x0300:
|
case 0x0300:
|
||||||
if (vendor_id != 0x1234)
|
if (vendor_id != 0x1234)
|
||||||
goto default_map;
|
goto default_map;
|
||||||
@ -398,6 +407,7 @@ void pci_bios_init(void)
|
|||||||
isa_outb(elcr[0], 0x4d0);
|
isa_outb(elcr[0], 0x4d0);
|
||||||
isa_outb(elcr[1], 0x4d1);
|
isa_outb(elcr[1], 0x4d1);
|
||||||
|
|
||||||
pci_for_each_device(pci_bios_init_device);
|
pci_bios_next_bus = 1;
|
||||||
|
pci_for_each_device(0, pci_bios_init_device);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -120,18 +120,12 @@ static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
|||||||
/* Don't know if this matches real hardware, but it agrees with OHW. */
|
/* Don't know if this matches real hardware, but it agrees with OHW. */
|
||||||
static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
|
static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
|
||||||
{
|
{
|
||||||
return (irq_num + (pci_dev->devfn >> 3)) & 3;
|
return (irq_num + (pci_dev->devfn >> 3)) & 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int prep_irq_levels[4];
|
|
||||||
|
|
||||||
static void prep_set_irq(void *pic, int irq_num, int level)
|
static void prep_set_irq(void *pic, int irq_num, int level)
|
||||||
{
|
{
|
||||||
int pic_irq_num;
|
pic_set_irq(irq_num ? 11 : 9, level);
|
||||||
prep_irq_levels[irq_num] = level;
|
|
||||||
level |= prep_irq_levels[irq_num ^ 2];
|
|
||||||
pic_irq_num = (irq_num == 0 || irq_num == 2) ? 9 : 11;
|
|
||||||
pic_set_irq(pic_irq_num, level);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
PCIBus *pci_prep_init(void)
|
PCIBus *pci_prep_init(void)
|
||||||
@ -141,7 +135,7 @@ PCIBus *pci_prep_init(void)
|
|||||||
int PPC_io_memory;
|
int PPC_io_memory;
|
||||||
|
|
||||||
s = qemu_mallocz(sizeof(PREPPCIState));
|
s = qemu_mallocz(sizeof(PREPPCIState));
|
||||||
s->bus = pci_register_bus(prep_set_irq, prep_map_irq, NULL, 0);
|
s->bus = pci_register_bus(prep_set_irq, prep_map_irq, NULL, 0, 2);
|
||||||
|
|
||||||
register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
|
register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
|
||||||
register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
|
register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
|
||||||
|
@ -161,7 +161,7 @@ PCIBus *pci_pmac_init(void *pic)
|
|||||||
/* Uninorth main bus */
|
/* Uninorth main bus */
|
||||||
s = qemu_mallocz(sizeof(UNINState));
|
s = qemu_mallocz(sizeof(UNINState));
|
||||||
s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
|
s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
|
||||||
pic, 11 << 3);
|
pic, 11 << 3, 4);
|
||||||
|
|
||||||
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
|
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
|
||||||
pci_unin_main_config_write, s);
|
pci_unin_main_config_write, s);
|
||||||
|
@ -11,7 +11,7 @@
|
|||||||
|
|
||||||
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
|
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
|
||||||
{
|
{
|
||||||
return addr & 0xf8ff;
|
return addr & 0xffffff;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
|
static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
|
||||||
@ -105,15 +105,15 @@ PCIBus *pci_vpb_init(void *pic, int irq, int realview)
|
|||||||
base = 0x40000000;
|
base = 0x40000000;
|
||||||
name = "Versatile/PB PCI Controller";
|
name = "Versatile/PB PCI Controller";
|
||||||
}
|
}
|
||||||
s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, pic, 11 << 3);
|
s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, pic, 11 << 3, 4);
|
||||||
/* ??? Register memory space. */
|
/* ??? Register memory space. */
|
||||||
|
|
||||||
mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
|
mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
|
||||||
pci_vpb_config_write, s);
|
pci_vpb_config_write, s);
|
||||||
/* Selfconfig area. */
|
/* Selfconfig area. */
|
||||||
cpu_register_physical_memory(base + 0x01000000, 0x10000, mem_config);
|
cpu_register_physical_memory(base + 0x01000000, 0x1000000, mem_config);
|
||||||
/* Normal config area. */
|
/* Normal config area. */
|
||||||
cpu_register_physical_memory(base + 0x02000000, 0x10000, mem_config);
|
cpu_register_physical_memory(base + 0x02000000, 0x1000000, mem_config);
|
||||||
|
|
||||||
d = pci_register_device(s, name, sizeof(PCIDevice), -1, NULL, NULL);
|
d = pci_register_device(s, name, sizeof(PCIDevice), -1, NULL, NULL);
|
||||||
|
|
||||||
|
6
vl.h
6
vl.h
@ -759,15 +759,17 @@ int pci_device_load(PCIDevice *s, QEMUFile *f);
|
|||||||
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
|
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
|
||||||
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
|
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
|
||||||
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
||||||
void *pic, int devfn_min);
|
void *pic, int devfn_min, int nirq);
|
||||||
|
|
||||||
void pci_nic_init(PCIBus *bus, NICInfo *nd);
|
void pci_nic_init(PCIBus *bus, NICInfo *nd);
|
||||||
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
|
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
|
||||||
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
|
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
|
||||||
int pci_bus_num(PCIBus *s);
|
int pci_bus_num(PCIBus *s);
|
||||||
void pci_for_each_device(void (*fn)(PCIDevice *d));
|
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
|
||||||
|
|
||||||
void pci_info(void);
|
void pci_info(void);
|
||||||
|
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
||||||
|
pci_map_irq_fn map_irq, const char *name);
|
||||||
|
|
||||||
/* prep_pci.c */
|
/* prep_pci.c */
|
||||||
PCIBus *pci_prep_init(void);
|
PCIBus *pci_prep_init(void);
|
||||||
|
Loading…
Reference in New Issue
Block a user