mirror of https://gitlab.com/qemu-project/qemu
hw/sd: add nuvoton MMC
Signed-off-by: Shengtan Mao <stmao@google.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Chris Rauer <crauer@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20211008002628.1958285-2-wuhaotsh@google.com> [rth: Fix typos of "nonexistent"] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -9,4 +9,5 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
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softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
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softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
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softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
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softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
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softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
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softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
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softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_sdhci.c'))
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softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
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softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
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@ -0,0 +1,182 @@
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/*
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* NPCM7xx SD-3.0 / eMMC-4.51 Host Controller
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*
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* Copyright (c) 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/sd/npcm7xx_sdhci.h"
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#include "migration/vmstate.h"
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#include "sdhci-internal.h"
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#include "qemu/log.h"
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static uint64_t npcm7xx_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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NPCM7xxSDHCIState *s = opaque;
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uint64_t val = 0;
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switch (addr) {
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case NPCM7XX_PRSTVALS_0:
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case NPCM7XX_PRSTVALS_1:
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case NPCM7XX_PRSTVALS_2:
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case NPCM7XX_PRSTVALS_3:
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case NPCM7XX_PRSTVALS_4:
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case NPCM7XX_PRSTVALS_5:
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val = s->regs.prstvals[(addr - NPCM7XX_PRSTVALS_0) / 2];
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break;
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case NPCM7XX_BOOTTOCTRL:
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val = s->regs.boottoctrl;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "SDHCI read of nonexistent reg: 0x%02"
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HWADDR_PRIx, addr);
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break;
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}
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return val;
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}
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static void npcm7xx_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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NPCM7xxSDHCIState *s = opaque;
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switch (addr) {
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case NPCM7XX_BOOTTOCTRL:
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s->regs.boottoctrl = val;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "SDHCI write of nonexistent reg: 0x%02"
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HWADDR_PRIx, addr);
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break;
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}
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}
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static bool npcm7xx_sdhci_check_mem_op(void *opaque, hwaddr addr,
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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switch (addr) {
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case NPCM7XX_PRSTVALS_0:
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case NPCM7XX_PRSTVALS_1:
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case NPCM7XX_PRSTVALS_2:
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case NPCM7XX_PRSTVALS_3:
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case NPCM7XX_PRSTVALS_4:
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case NPCM7XX_PRSTVALS_5:
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/* RO Word */
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return !is_write && size == 2;
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case NPCM7XX_BOOTTOCTRL:
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/* R/W Dword */
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return size == 4;
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default:
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return false;
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}
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}
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static const MemoryRegionOps npcm7xx_sdhci_ops = {
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.read = npcm7xx_sdhci_read,
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.write = npcm7xx_sdhci_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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.unaligned = false,
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.accepts = npcm7xx_sdhci_check_mem_op,
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},
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};
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static void npcm7xx_sdhci_realize(DeviceState *dev, Error **errp)
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{
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NPCM7xxSDHCIState *s = NPCM7XX_SDHCI(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
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memory_region_init(&s->container, OBJECT(s),
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"npcm7xx.sdhci-container", 0x1000);
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sysbus_init_mmio(sbd, &s->container);
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memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_sdhci_ops, s,
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TYPE_NPCM7XX_SDHCI, NPCM7XX_SDHCI_REGSIZE);
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memory_region_add_subregion_overlap(&s->container, NPCM7XX_PRSTVALS,
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&s->iomem, 1);
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sysbus_realize(sbd_sdhci, errp);
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(sbd_sdhci, 0));
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/* propagate irq and "sd-bus" from generic-sdhci */
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sysbus_pass_irq(sbd, sbd_sdhci);
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s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
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/* Set the read only preset values. */
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memset(s->regs.prstvals, 0, sizeof(s->regs.prstvals));
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s->regs.prstvals[0] = NPCM7XX_PRSTVALS_0_RESET;
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s->regs.prstvals[1] = NPCM7XX_PRSTVALS_1_RESET;
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s->regs.prstvals[3] = NPCM7XX_PRSTVALS_3_RESET;
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}
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static void npcm7xx_sdhci_reset(DeviceState *dev)
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{
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NPCM7xxSDHCIState *s = NPCM7XX_SDHCI(dev);
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device_cold_reset(DEVICE(&s->sdhci));
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s->regs.boottoctrl = 0;
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s->sdhci.prnsts = NPCM7XX_PRSNTS_RESET;
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s->sdhci.blkgap = NPCM7XX_BLKGAP_RESET;
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s->sdhci.capareg = NPCM7XX_CAPAB_RESET;
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s->sdhci.maxcurr = NPCM7XX_MAXCURR_RESET;
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s->sdhci.version = NPCM7XX_HCVER_RESET;
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}
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static const VMStateDescription vmstate_npcm7xx_sdhci = {
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.name = TYPE_NPCM7XX_SDHCI,
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.version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(regs.boottoctrl, NPCM7xxSDHCIState),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void npcm7xx_sdhci_class_init(ObjectClass *classp, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(classp);
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dc->desc = "NPCM7xx SD/eMMC Host Controller";
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dc->realize = npcm7xx_sdhci_realize;
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dc->reset = npcm7xx_sdhci_reset;
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dc->vmsd = &vmstate_npcm7xx_sdhci;
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}
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static void npcm7xx_sdhci_instance_init(Object *obj)
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{
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NPCM7xxSDHCIState *s = NPCM7XX_SDHCI(obj);
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object_initialize_child(OBJECT(s), "generic-sdhci", &s->sdhci,
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TYPE_SYSBUS_SDHCI);
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}
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static TypeInfo npcm7xx_sdhci_info = {
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.name = TYPE_NPCM7XX_SDHCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxSDHCIState),
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.instance_init = npcm7xx_sdhci_instance_init,
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.class_init = npcm7xx_sdhci_class_init,
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};
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static void npcm7xx_sdhci_register_types(void)
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{
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type_register_static(&npcm7xx_sdhci_info);
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}
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type_init(npcm7xx_sdhci_register_types)
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@ -0,0 +1,65 @@
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/*
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* NPCM7xx SD-3.0 / eMMC-4.51 Host Controller
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*
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* Copyright (c) 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_SDHCI_H
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#define NPCM7XX_SDHCI_H
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#include "hw/sd/sdhci.h"
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#include "qom/object.h"
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#define TYPE_NPCM7XX_SDHCI "npcm7xx.sdhci"
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#define NPCM7XX_PRSTVALS_SIZE 6
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#define NPCM7XX_PRSTVALS 0x60
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#define NPCM7XX_PRSTVALS_0 0x0
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#define NPCM7XX_PRSTVALS_1 0x2
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#define NPCM7XX_PRSTVALS_2 0x4
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#define NPCM7XX_PRSTVALS_3 0x6
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#define NPCM7XX_PRSTVALS_4 0x8
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#define NPCM7XX_PRSTVALS_5 0xA
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#define NPCM7XX_BOOTTOCTRL 0x10
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#define NPCM7XX_SDHCI_REGSIZE 0x20
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#define NPCM7XX_PRSNTS_RESET 0x04A00000
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#define NPCM7XX_BLKGAP_RESET 0x80
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#define NPCM7XX_CAPAB_RESET 0x0100200161EE0399
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#define NPCM7XX_MAXCURR_RESET 0x0000000000000005
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#define NPCM7XX_HCVER_RESET 0x1002
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#define NPCM7XX_PRSTVALS_0_RESET 0x0040
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#define NPCM7XX_PRSTVALS_1_RESET 0x0001
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#define NPCM7XX_PRSTVALS_3_RESET 0x0001
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OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSDHCIState, NPCM7XX_SDHCI)
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typedef struct NPCM7xxRegs {
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/* Preset Values Register Field, read-only */
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uint16_t prstvals[NPCM7XX_PRSTVALS_SIZE];
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/* Boot Timeout Control Register, read-write */
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uint32_t boottoctrl;
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} NPCM7xxRegisters;
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typedef struct NPCM7xxSDHCIState {
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SysBusDevice parent;
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MemoryRegion container;
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MemoryRegion iomem;
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BusState *bus;
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NPCM7xxRegisters regs;
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SDHCIState sdhci;
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} NPCM7xxSDHCIState;
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#endif /* NPCM7XX_SDHCI_H */
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