target/mips: Add emulation of nanoMIPS 16-bit logic instructions
Add emulation of NOT16, AND16, XOR16, OR16 instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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@ -16760,6 +16760,37 @@ static inline int decode_gpr_gpr4_zero(int r)
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/* extraction utilities */
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#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
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#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
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#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
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#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
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#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
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#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
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static void gen_pool16c_nanomips_insn(DisasContext *ctx)
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{
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int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
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int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
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switch (extract32(ctx->opcode, 2, 2)) {
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case NM_NOT16:
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gen_logic(ctx, OPC_NOR, rt, rs, 0);
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break;
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case NM_AND16:
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gen_logic(ctx, OPC_AND, rt, rt, rs);
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break;
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case NM_XOR16:
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gen_logic(ctx, OPC_XOR, rt, rt, rs);
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break;
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case NM_OR16:
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gen_logic(ctx, OPC_OR, rt, rt, rs);
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break;
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}
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}
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static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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{
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uint32_t op;
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@ -16836,6 +16867,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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case NM_P16C:
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switch (ctx->opcode & 1) {
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case NM_POOL16C_0:
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gen_pool16c_nanomips_insn(ctx);
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break;
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case NM_LWXS16:
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gen_ldxs(ctx, rt, rs, rd);
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@ -16910,6 +16942,12 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_ANDI16:
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{
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uint32_t u = extract32(ctx->opcode, 0, 4);
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u = (u == 12) ? 0xff :
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(u == 13) ? 0xffff : u;
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gen_logic_imm(ctx, OPC_ANDI, rt, rs, u);
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}
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break;
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case NM_P16_LB:
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offset = extract32(ctx->opcode, 0, 2);
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