arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -572,3 +572,21 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
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{
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return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
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}
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/*
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* AdvSIMD half-precision
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*/
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#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
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#define ADVSIMD_HALFOP(name) \
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float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
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{ \
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float_status *fpst = fpstp; \
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return float16_ ## name(a, b, fpst); \
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}
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ADVSIMD_HALFOP(min)
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ADVSIMD_HALFOP(max)
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ADVSIMD_HALFOP(minnum)
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ADVSIMD_HALFOP(maxnum)
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@ -48,3 +48,7 @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
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i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
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DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
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DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
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DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
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@ -5741,26 +5741,75 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_resh);
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}
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static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
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int opc, bool is_min, TCGv_ptr fpst)
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/*
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* do_reduction_op helper
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*
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* This mirrors the Reduce() pseudocode in the ARM ARM. It is
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* important for correct NaN propagation that we do these
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* operations in exactly the order specified by the pseudocode.
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*
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* This is a recursive function, TCG temps should be freed by the
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* calling function once it is done with the values.
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*/
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static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
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int esize, int size, int vmap, TCGv_ptr fpst)
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{
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/* Helper function for disas_simd_across_lanes: do a single precision
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* min/max operation on the specified two inputs,
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* and return the result in tcg_elt1.
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*/
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if (opc == 0xc) {
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if (is_min) {
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gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
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} else {
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gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
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}
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if (esize == size) {
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int element;
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TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
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TCGv_i32 tcg_elem;
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/* We should have one register left here */
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assert(ctpop8(vmap) == 1);
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element = ctz32(vmap);
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assert(element < 8);
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tcg_elem = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_elem, rn, element, msize);
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return tcg_elem;
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} else {
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assert(opc == 0xf);
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if (is_min) {
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gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
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} else {
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gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
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int bits = size / 2;
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int shift = ctpop8(vmap) / 2;
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int vmap_lo = (vmap >> shift) & vmap;
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int vmap_hi = (vmap & ~vmap_lo);
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TCGv_i32 tcg_hi, tcg_lo, tcg_res;
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tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
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tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
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tcg_res = tcg_temp_new_i32();
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switch (fpopcode) {
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case 0x0c: /* fmaxnmv half-precision */
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gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x0f: /* fmaxv half-precision */
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gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x1c: /* fminnmv half-precision */
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gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x1f: /* fminv half-precision */
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gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x2c: /* fmaxnmv */
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gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x2f: /* fmaxv */
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gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x3c: /* fminnmv */
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gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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case 0x3f: /* fminv */
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gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free_i32(tcg_hi);
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tcg_temp_free_i32(tcg_lo);
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return tcg_res;
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}
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}
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@ -5802,16 +5851,21 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
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break;
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case 0xc: /* FMAXNMV, FMINNMV */
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case 0xf: /* FMAXV, FMINV */
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if (!is_u || !is_q || extract32(size, 0, 1)) {
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unallocated_encoding(s);
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return;
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}
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/* Bit 1 of size field encodes min vs max, and actual size is always
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* 32 bits: adjust the size variable so following code can rely on it
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/* Bit 1 of size field encodes min vs max and the actual size
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* depends on the encoding of the U bit. If not set (and FP16
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* enabled) then we do half-precision float instead of single
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* precision.
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*/
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is_min = extract32(size, 1, 1);
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is_fp = true;
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size = 2;
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if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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size = 1;
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} else if (!is_u || !is_q || extract32(size, 0, 1)) {
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unallocated_encoding(s);
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return;
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} else {
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size = 2;
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}
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break;
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default:
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unallocated_encoding(s);
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@ -5868,38 +5922,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
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}
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} else {
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/* Floating point ops which work on 32 bit (single) intermediates.
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/* Floating point vector reduction ops which work across 32
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* bit (single) or 16 bit (half-precision) intermediates.
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* Note that correct NaN propagation requires that we do these
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* operations in exactly the order specified by the pseudocode.
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*/
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TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
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TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
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TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
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TCGv_ptr fpst = get_fpstatus_ptr(false);
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assert(esize == 32);
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assert(elements == 4);
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read_vec_element(s, tcg_elt, rn, 0, MO_32);
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tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
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read_vec_element(s, tcg_elt, rn, 1, MO_32);
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tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
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do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
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read_vec_element(s, tcg_elt, rn, 2, MO_32);
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tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
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read_vec_element(s, tcg_elt, rn, 3, MO_32);
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tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
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do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
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do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
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tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
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tcg_temp_free_i32(tcg_elt1);
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tcg_temp_free_i32(tcg_elt2);
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tcg_temp_free_i32(tcg_elt3);
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TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
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int fpopcode = opcode | is_min << 4 | is_u << 5;
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int vmap = (1 << elements) - 1;
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TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
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(is_q ? 128 : 64), vmap, fpst);
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tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
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tcg_temp_free_i32(tcg_res32);
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tcg_temp_free_ptr(fpst);
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}
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