mirror of https://gitlab.com/qemu-project/qemu
armsse: Rename QOM macros to avoid conflicts
Rename TYPE_ARMSSE to TYPE_ARM_SSE, and ARMSSE*() type checking macros to ARM_SSE*(). This will avoid a future conflict between an ARM_SSE() type checking macro and the ARMSSE typedef name. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-26-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -167,7 +167,7 @@ static void irq_status_forwarder(void *opaque, int n, int level)
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static void nsccfg_handler(void *opaque, int n, int level)
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static void nsccfg_handler(void *opaque, int n, int level)
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{
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{
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ARMSSE *s = ARMSSE(opaque);
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ARMSSE *s = ARM_SSE(opaque);
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s->nsccfg = level;
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s->nsccfg = level;
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}
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}
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@ -233,8 +233,8 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
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static void armsse_init(Object *obj)
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static void armsse_init(Object *obj)
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{
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{
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ARMSSE *s = ARMSSE(obj);
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ARMSSE *s = ARM_SSE(obj);
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ARMSSEClass *asc = ARMSSE_GET_CLASS(obj);
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ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj);
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const ARMSSEInfo *info = asc->info;
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const ARMSSEInfo *info = asc->info;
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int i;
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int i;
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@ -391,7 +391,7 @@ static void armsse_exp_irq(void *opaque, int n, int level)
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static void armsse_mpcexp_status(void *opaque, int n, int level)
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static void armsse_mpcexp_status(void *opaque, int n, int level)
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{
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{
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ARMSSE *s = ARMSSE(opaque);
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ARMSSE *s = ARM_SSE(opaque);
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qemu_set_irq(s->mpcexp_status_in[n], level);
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qemu_set_irq(s->mpcexp_status_in[n], level);
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}
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}
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@ -401,7 +401,7 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno)
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* Return a qemu_irq which can be used to signal IRQ n to
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* Return a qemu_irq which can be used to signal IRQ n to
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* all CPUs in the SSE.
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* all CPUs in the SSE.
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*/
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*/
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ARMSSEClass *asc = ARMSSE_GET_CLASS(s);
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ARMSSEClass *asc = ARM_SSE_GET_CLASS(s);
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const ARMSSEInfo *info = asc->info;
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const ARMSSEInfo *info = asc->info;
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assert(irq_is_common[irqno]);
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assert(irq_is_common[irqno]);
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@ -428,8 +428,8 @@ static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr)
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static void armsse_realize(DeviceState *dev, Error **errp)
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static void armsse_realize(DeviceState *dev, Error **errp)
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{
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{
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ARMSSE *s = ARMSSE(dev);
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ARMSSE *s = ARM_SSE(dev);
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ARMSSEClass *asc = ARMSSE_GET_CLASS(dev);
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ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev);
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const ARMSSEInfo *info = asc->info;
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const ARMSSEInfo *info = asc->info;
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int i;
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int i;
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MemoryRegion *mr;
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MemoryRegion *mr;
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@ -1114,7 +1114,7 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
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* of the address bits. The NSC attribute is guest-adjustable via the
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* of the address bits. The NSC attribute is guest-adjustable via the
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* NSCCFG register in the security controller.
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* NSCCFG register in the security controller.
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*/
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*/
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ARMSSE *s = ARMSSE(ii);
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ARMSSE *s = ARM_SSE(ii);
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int region = extract32(address, 28, 4);
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int region = extract32(address, 28, 4);
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*ns = !(region & 1);
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*ns = !(region & 1);
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@ -1136,7 +1136,7 @@ static const VMStateDescription armsse_vmstate = {
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static void armsse_reset(DeviceState *dev)
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static void armsse_reset(DeviceState *dev)
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{
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{
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ARMSSE *s = ARMSSE(dev);
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ARMSSE *s = ARM_SSE(dev);
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s->nsccfg = 0;
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s->nsccfg = 0;
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}
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}
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@ -1145,7 +1145,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass);
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IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass);
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ARMSSEClass *asc = ARMSSE_CLASS(klass);
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ARMSSEClass *asc = ARM_SSE_CLASS(klass);
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const ARMSSEInfo *info = data;
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const ARMSSEInfo *info = data;
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dc->realize = armsse_realize;
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dc->realize = armsse_realize;
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@ -1157,7 +1157,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
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}
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}
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static const TypeInfo armsse_info = {
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static const TypeInfo armsse_info = {
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.name = TYPE_ARMSSE,
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.name = TYPE_ARM_SSE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMSSE),
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.instance_size = sizeof(ARMSSE),
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.instance_init = armsse_init,
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.instance_init = armsse_init,
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@ -1177,7 +1177,7 @@ static void armsse_register_types(void)
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for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) {
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for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) {
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TypeInfo ti = {
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TypeInfo ti = {
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.name = armsse_variants[i].name,
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.name = armsse_variants[i].name,
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.parent = TYPE_ARMSSE,
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.parent = TYPE_ARM_SSE,
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.class_init = armsse_class_init,
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.class_init = armsse_class_init,
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.class_data = (void *)&armsse_variants[i],
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.class_data = (void *)&armsse_variants[i],
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};
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};
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@ -106,8 +106,8 @@
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#include "hw/core/split-irq.h"
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#include "hw/core/split-irq.h"
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#include "hw/cpu/cluster.h"
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#include "hw/cpu/cluster.h"
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#define TYPE_ARMSSE "arm-sse"
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#define TYPE_ARM_SSE "arm-sse"
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#define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
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#define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE)
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/*
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/*
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* These type names are for specific IoTKit subsystems; other than
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* These type names are for specific IoTKit subsystems; other than
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@ -224,9 +224,9 @@ typedef struct ARMSSEClass {
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const ARMSSEInfo *info;
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const ARMSSEInfo *info;
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} ARMSSEClass;
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} ARMSSEClass;
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#define ARMSSE_CLASS(klass) \
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#define ARM_SSE_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE)
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OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE)
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#define ARMSSE_GET_CLASS(obj) \
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#define ARM_SSE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE)
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OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARM_SSE)
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#endif
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#endif
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