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target/riscv: Use gen_arith_per_ol for RVM

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The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-11-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-10-19 20:17:04 -07:00 committed by Alistair Francis
parent 7667cafd5a
commit 80347ae9f2
2 changed files with 39 additions and 3 deletions
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26
target/riscv/insn_trans/trans_rvm.c.inc
View File

@ -33,10 +33,16 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
tcg_temp_free(discard);
}
static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_mul_tl(ret, s1, s2);
tcg_gen_sari_tl(ret, ret, 32);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE, gen_mulh);
return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w);
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@ -54,10 +60,23 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_ext32s_tl(t1, arg1);
tcg_gen_ext32u_tl(t2, arg2);
tcg_gen_mul_tl(ret, t1, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_gen_sari_tl(ret, ret, 32);
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w);
}
static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@ -71,7 +90,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
/* gen_mulh_w works for either sign as input. */
return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)

16
target/riscv/translate.c
View File

@ -403,6 +403,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
return true;
}
static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
void (*f_tl)(TCGv, TCGv, TCGv),
void (*f_32)(TCGv, TCGv, TCGv))
{
int olen = get_olen(ctx);
if (olen != TARGET_LONG_BITS) {
if (olen == 32) {
f_tl = f_32;
} else {
g_assert_not_reached();
}
}
return gen_arith(ctx, a, ext, f_tl);
}
static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{